file_write HDL Worker

Application HDL worker that only runs on FPGA simulator platforms. This worker will not run or be built for any FPGA hardware platforms because it contains code that cannot be realized into RTL.

Detail

Worker Properties

• fileName

  • Type: string

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: True

    • Volatile: False

    • Read back: True

  • Default value: None

• CWD_MAX_LENGTH: The maximum string length for cwd.

  • Type: ulong

  • Access:

    • Parameter: True

    • Writable: False

    • Initial: False

    • Volatile: False

    • Read back: False

  • Default value: 512

• cwd: The current working directory of the application (required for HDL worker; cannot be determined automatically).

  • Type: string

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

Worker Ports

Inputs:

• in: Data written to file.

  • Type: streaminterface

  • Protocol: None

  • Optional: False