N310 CPLD SPI Interface (n310_cpld_spi)

SPI communication interface for the Master CPLD Controller on each daughterboard. This device worker supports register map programming of the following hardware chips: CPLD, Clock Source, and TX/RX LO Synthesizers. Each hardware chip has a unique SPI frame structure.

Design

Interface

<ComponentSpec>
  <property name='CPLD_DB_SEL' type='bool' writable='true' default='true' description='Daughterboard (DB) Selection: ``0`` or ``false`` = DBA, ``1`` or ``true`` = DBB'/>
  <property name='CPLD_FRAME' type='ulong' writable='true' volatile='true' description='SPI Frame'/>
  <property name='CPLD_RENABLE' type='bool' writable='true' default='false' description='SPI Read Enable'/>
  <property name='CPLD_WENABLE' type='bool' writable='true' default='false' description='SPI Write Enable'/>
  <property name='CPLD_DONE' type='bool' writable='true' volatile='true' description='SPI Transfer Done Flag'/>
  <property name='CPLD_ADDR_CS' type='uchar' writable='true' description='Chip Selection: ``000`` = CPLD, ``001`` = LMK, ``011`` = TX LO SYN, ``100`` RX LO SYN'/>
  <property name='CPLD_RDATA' type='ushort' writable='true' volatile='true' description='Readback Register Value'/>
</ComponentSpec>

Properties

  • CPLD_DB_SEL: Daughterboard (DB) Selection: 0 or false = DBA, 1 or true = DBB.

    • Type: bool

    • Access:

      • Parameter: False

      • Writable: True

      • Initial: False

      • Volatile: False

    • Default value: true

  • CPLD_FRAME: SPI Frame.

    • Type: ulong

    • Access:

      • Parameter: False

      • Writable: True

      • Initial: False

      • Volatile: True

    • Default value: None

  • CPLD_RENABLE: SPI Read Enable.

    • Type: bool

    • Access:

      • Parameter: False

      • Writable: True

      • Initial: False

      • Volatile: False

    • Default value: false

  • CPLD_WENABLE: SPI Write Enable.

    • Type: bool

    • Access:

      • Parameter: False

      • Writable: True

      • Initial: False

      • Volatile: False

    • Default value: false

  • CPLD_DONE: SPI Transfer Done Flag.

    • Type: bool

    • Access:

      • Parameter: False

      • Writable: True

      • Initial: False

      • Volatile: True

    • Default value: None

  • CPLD_ADDR_CS: Chip Selection: 000 = CPLD, 001 = LMK, 011 = TX LO SYN, 100 RX LO SYN.

    • Type: uchar

    • Access:

      • Parameter: False

      • Writable: True

      • Initial: False

      • Volatile: False

    • Default value: None

  • CPLD_RDATA: Readback Register Value.

    • Type: ushort

    • Access:

      • Parameter: False

      • Writable: True

      • Initial: False

      • Volatile: True

    • Default value: None

Implementations

Dependencies

There is also a dependency on:

  • ieee.std_logic_1164

  • ieee.numeric_std

Limitations

Limitations of n310_cpld_spi are:

  • NONE