cic_int_csts HDL Worker
Detail
The HDL implementation of cic_dec_csts device workers, which implements the CIC interpolator primitive, with two instances declared, one for the real data values and the second for the imaginary data values. While the CIC filter stages are completed within the child primitive, the attenuation before the final output is done in the worker.
This device worker implements a BY-PASS Mode: down_sample_factor = 1.
Worker Properties
VIVADO_ILA_p: Build-time parameter for Xilinx Integrated Logic Analyzer (ILA).Type:
boolAccess:
Parameter:
TrueWritable:
FalseInitial:
FalseVolatile:
FalseRead back:
False
Default value:
None
ocpi_buffer_size_output: OpenCPI Framework Property.Type:
ushortAccess:
Parameter:
FalseWritable:
FalseInitial:
TrueVolatile:
FalseRead back:
False
Default value:
0
ocpi_blocked_output: OpenCPI Framework Property.Type:
ulongAccess:
Parameter:
FalseWritable:
FalseInitial:
FalseVolatile:
TrueRead back:
False
Default value:
None
ocpi_max_latency_output: OpenCPI Framework Property.Type:
ushortAccess:
Parameter:
TrueWritable:
FalseInitial:
FalseVolatile:
FalseRead back:
False
Default value:
None
ocpi_latency_output: OpenCPI Framework Property.Type:
ushortAccess:
Parameter:
FalseWritable:
FalseInitial:
FalseVolatile:
TrueRead back:
False
Default value:
None
ocpi_messages_output: OpenCPI Framework Property.Type:
ulongAccess:
Parameter:
FalseWritable:
FalseInitial:
FalseVolatile:
TrueRead back:
False
Default value:
None
ocpi_bytes_output: OpenCPI Framework Property.Type:
ulongAccess:
Parameter:
FalseWritable:
FalseInitial:
FalseVolatile:
TrueRead back:
False
Default value:
None
Worker Ports
input: Input Data Port.Protocol:
complex_short_timed_sampleOptional:
False
output: Output Data Port.Protocol:
complex_short_timed_sampleOptional:
False
Inputs:
Outputs: