z3u_i2c_bus1 HDL worker

Implementation of the z3u_i2c_bus1 HDL worker for the OpenCPI i2c state-machine.

Detail

The z3u_i2c_bus1 HDL subdevice worker is specific to the Matchstiq Z3U platform. It instances three pcal6524 workers on the bus. Each of the workers utilize raw properties to access the bare device and are indexed according to the SLAVE_ADDRESS_p indices located in the z3u_i2c_bus1-build.xml. The CLK_FREQ_p parameter declares the expected frequency of the control plane clock.

Review of the Epiq Solutions Matchstiq-Z3u Hardware Users Manual determined that the I2C SCL rate should be set to 100kHz.

I2C Bus2 Addressing

Worker	Index	Address
pcal6524	0	0x20
pcal6524	1	0x21
pcal6524	2	0x22

Control Timing and Signals

The z3u_i2c_bus1 device worker follows the same implementation scheme as other examples within FOSS. Which is to say that the expected control plane clock rate is 100MHz and the desired I2C SCL is determine by setting the CLK_CNT generic of the i2c_opencore_ctrl instance. For example, if the desired I2C SCL frequency is 100kHz, then the CLK_CNT is set per the following.

CLK_CNT => to_unsigned(from_float(CLK_FREQ_p)/100000,16) ) -- I2C clk = ~ 100kHz