data_sink_qdac HDL Device Worker
HDL device worker implementation providing common functionality to all DAC device types.
Detail
Be sure to check the samp_count_before_first_underrun and num_underruns component properties
at the end of an application run because they are not stable until then. The worker does not use
clock domain crossing (cdc) HDL primitive library circuits
for these properties because it takes
advantage of the fact that they will have a stable value by the time the OpenCPI control
plane reads them at the end of an application run.
Worker Properties
IN_PORT_DATA_WIDTHType:
ulongAccess:
Parameter:
TrueWritable:
FalseInitial:
FalseVolatile:
FalseRead back:
False
Default value:
32
unused_opcode_detected_stickyType:
boolAccess:
Parameter:
FalseWritable:
FalseInitial:
FalseVolatile:
TrueRead back:
False
Default value:
None
clr_unused_opcode_detected_stickyType:
boolAccess:
Parameter:
FalseWritable:
TrueInitial:
FalseVolatile:
FalseRead back:
False
Default value:
None
dac_clk_freq_hzType:
floatAccess:
Parameter:
TrueWritable:
FalseInitial:
FalseVolatile:
FalseRead back:
False
Default value:
1e6
statusType:
ushortAccess:
Parameter:
FalseWritable:
FalseInitial:
FalseVolatile:
TrueRead back:
False
Default value:
None
ctl_countType:
ulongAccess:
Parameter:
FalseWritable:
FalseInitial:
FalseVolatile:
TrueRead back:
False
Default value:
None
dac_countType:
ulongAccess:
Parameter:
FalseWritable:
FalseInitial:
FalseVolatile:
TrueRead back:
False
Default value:
None
Worker Ports
in: Size defined byIN_PORT_DATA_WIDTH.Type:
streaminterfaceData width:
IN_PORT_DATA_WIDTHProtocol:
ComplexShortWithMetadata-protOptional:
False
on_off: See the OpenCPI HDL Development Guide for instructions on calculating the default value.Type:
streaminterfaceProtocol:
tx_event-protOptional:
True
devType:
devsignalMaster:
trueCount:
1Optional:
falseSignals:
clkdata_idata_qvalidpresent
Inputs:
Outputs:
Interfaces:
Utilization
Utilization reporting is not currently implemented.