data_sink_qdac HDL Device Worker

HDL device worker implementation providing common functionality to all DAC device types.

Detail

Be sure to check the samp_count_before_first_underrun and num_underruns component properties at the end of an application run because they are not stable until then. The worker does not use clock domain crossing (cdc) HDL primitive library circuits for these properties because it takes advantage of the fact that they will have a stable value by the time the OpenCPI control plane reads them at the end of an application run.

Worker Properties

  • IN_PORT_DATA_WIDTH

    • Type: ulong

    • Access:

      • Parameter: True

      • Writable: False

      • Initial: False

      • Volatile: False

      • Read back: False

    • Default value: 32

  • unused_opcode_detected_sticky

    • Type: bool

    • Access:

      • Parameter: False

      • Writable: False

      • Initial: False

      • Volatile: True

      • Read back: False

    • Default value: None

  • clr_unused_opcode_detected_sticky

    • Type: bool

    • Access:

      • Parameter: False

      • Writable: True

      • Initial: False

      • Volatile: False

      • Read back: False

    • Default value: None

  • dac_clk_freq_hz

    • Type: float

    • Access:

      • Parameter: True

      • Writable: False

      • Initial: False

      • Volatile: False

      • Read back: False

    • Default value: 1e6

  • status

    • Type: ushort

    • Access:

      • Parameter: False

      • Writable: False

      • Initial: False

      • Volatile: True

      • Read back: False

    • Default value: None

  • ctl_count

    • Type: ulong

    • Access:

      • Parameter: False

      • Writable: False

      • Initial: False

      • Volatile: True

      • Read back: False

    • Default value: None

  • dac_count

    • Type: ulong

    • Access:

      • Parameter: False

      • Writable: False

      • Initial: False

      • Volatile: True

      • Read back: False

    • Default value: None

Worker Ports

    Inputs:

  • in: Size defined by IN_PORT_DATA_WIDTH.

    • Type: streaminterface

    • Data width: IN_PORT_DATA_WIDTH

    • Protocol: ComplexShortWithMetadata-prot

    • Optional: False

  • Outputs:

  • on_off: See the OpenCPI HDL Development Guide for instructions on calculating the default value.

    • Type: streaminterface

    • Protocol: tx_event-prot

    • Optional: True

  • Interfaces:

  • dev

    • Type: devsignal

    • Master: true

    • Count: 1

    • Optional: false

    • Signals:

      • clk

      • data_i

      • data_q

      • valid

      • present

Utilization

Utilization reporting is not currently implemented.