Data Sink QDAC (data_sink_qdac)

Provides HDL device worker functionality common to all DAC devices. data_sink_qdac is an asset in the ocpi.platform.devices component library. Implementations include the data_sink_qdac HDL Device Worker (data_sink_qdac.hdl). Tested platforms include xsim.

Design

The data sink Quad Digital-to-Analog-Converter (QDAC) component provides the properties and ports necessary for its HDL device worker implementation, which provides the functionality that is common to all Digital-to-Analog Converter (DAC) device types. This functionality includes:

  • Interpreting input messages indicating end of data and finishing on end-of-file (EOF)

  • Normalizing input data to the bit width of the device

  • Providing an underrun indicator when the rate of input data is less than the DAC data rate

The data sink QDAC HDL device worker implementation is intended to be paired with an HDL subdevice worker that translates the dev interface to a device-specific interface.

A block diagram representation of the implementation is given in Figure 1:

Data Sink QDAC Block Diagram

Figure 1: Data Sink QDAC Block Diagram

Interface

<ComponentSpec>
  <Property Name="DAC_WIDTH_BITS"
            Type="UChar"
            Parameter="True"
            Default="12"
            Description="Number of bits in each of the I and Q values delivered to the DAC device"/>
  <Property Name="DAC_OUTPUT_IS_LSB_OF_IN_PORT" 
            Type="Bool" 
            Parameter="True"
	    Default="false"
            Description="Indicates whether DAC data is extracted from the most
                         significant or least significant DAC_WIDTH_BITS of the in port."/>
  <Property Name="underrun_sticky_error"
            Type="Bool"
            Volatile="true"
            Description="Sticky bit indication of samples underrun."/>
  <Property Name="clr_underrun_sticky_error" 
            Type="Bool"
            Writable="true"
            Description="Writing true clears underrun_sticky_error."/>
  <Property name='samp_count_before_first_underrun'
            type='ulong'
            volatile='true'
            description='Number of samples before the first sample underrun.'/>
  <Property name='num_underruns'
            type='ulong'
            volatile='true'
            description='Number of sample underruns.'/>

  <Port Name="in" 
        Protocol="ComplexShortWithMetadata-prot"/>
  <Port Name="on_off" 
        Protocol="tx_event-prot"
        Optional="1"
        Producer="true"/>
</ComponentSpec>

Properties

  • DAC_WIDTH_BITS: Number of bits in each of the I and Q values delivered to the DAC device.

    • Type: uchar

    • Access:

      • Parameter: True

      • Writable: False

      • Initial: False

      • Volatile: False

    • Default value: 12

  • DAC_OUTPUT_IS_LSB_OF_IN_PORT: Indicates whether DAC data is extracted from the most significant or least significant DAC_WIDTH_BITS of the in port.

    • Type: bool

    • Access:

      • Parameter: True

      • Writable: False

      • Initial: False

      • Volatile: False

    • Default value: false

  • underrun_sticky_error: Sticky bit indication of samples underrun.

    • Type: bool

    • Access:

      • Parameter: False

      • Writable: False

      • Initial: False

      • Volatile: True

    • Default value: None

  • clr_underrun_sticky_error: Writing true clears underrun_sticky_error.

    • Type: bool

    • Access:

      • Parameter: False

      • Writable: True

      • Initial: False

      • Volatile: False

    • Default value: None

  • samp_count_before_first_underrun: Number of samples before the first sample underrun.

    • Type: ulong

    • Access:

      • Parameter: False

      • Writable: False

      • Initial: False

      • Volatile: True

    • Default value: None

  • num_underruns: Number of sample underruns.

    • Type: ulong

    • Access:

      • Parameter: False

      • Writable: False

      • Initial: False

      • Volatile: True

    • Default value: None

Ports

Inputs:

  • in

    • Protocol: ComplexShortWithMetadata-prot

    • Optional: False

Outputs:

  • on_off

    • Protocol: tx_event-prot

    • Optional: True

Implementations

  • data_sink_qdac (HDL)

    HDL device worker implementation providing common functionality to all DAC device types.

Example Application

To be supplied: a meaningful example for this HDL device worker.

<?xml version="1.0"?>
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     distributed with this source distribution.

     This file is part of OpenCPI <http://www.opencpi.org>

     OpenCPI is free software: you can redistribute it and/or modify it under
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     FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for
     more details.

     You should have received a copy of the GNU Lesser General Public License
     along with this program. If not, see <http://www.gnu.org/licenses/>. -->
<application done="file_write">
  <instance component="ocpi.core.file_read" connect="data_sink_qdac">
    <property name="filename" value="input.bin"/>
  </instance>
  <instance component="ocpi.platform.devices.data_sink_qdac" connect="file_write">
    <!-- Skeleton application outline, set properties here. Or change this
         example application to do something more real-world appropriate if
         file-read, then component, then file-write is too artifical to be a
         useful example. -->
  </instance>
  <instance component="ocpi.core.file_write">
    <property name="filename" value="output.bin"/>
  </instance>
</application>

Dependencies

The dependencies on other elements in OpenCPI are:

  • None.

Limitations

Limitations of data_sink_qdac are:

  • None.

Testing

This component test suite uses the OpenCPI unit test framework, which uses a device emulator worker for verification. The device emulator worker produces clocks of varying frequency from 1e6 to 200e6 Hz which are forwarded to the dev port of the unit under test. The unit test checks that the input file and output file match and that no expected underruns occurred during the test.

Component testing not completed.