FSK (n310_fsk)

Description

This application will be deprecated within this OSP in future releases.

n310 implementation for the FSK reference design. The only modifications to the reference design are the updated interpolation and decimation factors due to the higher sampling rate of the n310 platform. This application verifies the running of the FSK reference design on the n310 platform using the following OpenCPI Application Specifications (OAS):

  • n310_fsk_tx.xml - Transmitter

  • n310_fsk_rx.xml - Receiver

  • n310_fsk_txrx.xml - Transceiver

  • n310_fsk_loopback.xml - Transceiver Baseband Loopback

  • n310_fsk_filerw.xml - RCC Only

Build

  1. Ensure the following ocpi.assets components are build for the n310 platform:

    • ocpi.assets.comms_comps.mfsk_mapper.hdl

    • ocpi.assets.util_comps.zero_pad.hdl

    • ocpi.assets.dsp_comps.fir_real_sse.hdl

    • ocpi.assets.dsp_comps.phase_to_amp_cordic.hdl

    • ocpi.assets.dsp_comps.cic_int.hdl

    • ocpi.assets.misc_comps.iqstream_to_csts.hdl

    • ocpi.assets.misc_comps.csts_to_iqstream.hdl

    • ocpi.assets.dsp_comps.dc_offset_filter.hdl

    • ocpi.assets.dsp_comps.iq_imbalance_fixer.hdl

    • ocpi.assets.dsp_comps.complex_mixer.hdl

    • ocpi.assets.dsp_comps.cic_dec.hdl

    • ocpi.assets.dsp_comps.rp_cordic.hdl

    • cpi.assets.dsp_comps.fir_real_sse.hdl

  2. Ensure the following ocpi.assets components are build for the ettus_n310_v4 platform:

    • ocpi.assets.dsp_comps.Baudtracking_simple.rcc.0.ettus_n310_v4.so

    • ocpi.assets.dsp_comps.real_digitizer.rcc.0.ettus_n310_v4.so

  1. Build the following assemblies using ocpidev build --hdl-plaform n310 within each assemblies directory (./hdl/assemblies):

    • n310_fsk_tx

    • n310_fsk_rx

    • n310_fsk_txrx

    • n310_fsk_loopback

  2. Build the application using ocpidev build --rcc-platform ettus_n310_v4 within the application directory. The application artifact is ./target-ettus_n310_v4/n310_fsk.

Prerequisites

  1. Copy the following ocpi.assets artifacts into the OpenCPI artifacts directory (/home/root/opencpi/artifacts) on the n310 platform:

    • ocpi.assets.dsp_comps.Baudtracking_simple.rcc.0.ettus_n310_v4.so

    • ocpi.assets.dsp_comps.real_digitizer.rcc.0.ettus_n310_v4.so

  2. Copy DRC artifacts into the OpenCPI artifacts directory (/home/root/opencpi/artifacts) on the n310 platform:

    • ocpi.osp.n3xx.devices.drc_n310.rcc.10.ettus_n310_v4.so (n310_fsk_txrx.xml and n310_fsk_loopback.xml)

    • ocpi.osp.n3xx.devices.drc_n310.rcc.11.ettus_n310_v4.so (n310_fsk_tx.xml)

    • ocpi.osp.n3xx.devices.drc_n310.rcc.12.ettus_n310_v4.so (n310_fsk_rx.xml)

  3. Make bitz directory within the application working directory on the n310 platform:

% mkdir ./bitz

  1. Copy the following the bitz files in the ./artifacts directory into the bitz directory in the application working directory:

    • ocpi.osp.n3xx.fsk_tx_n310_cfg_1tx_0rx_dba_cnt_1tx_0rx_nocic_dba.hdl.0.n310.bitz

    • ocpi.osp.n3xx.fsk_rx_n310_cfg_0tx_1rx_dba_cnt_0tx_1rx_nocic_dba.hdl.0.n310.bitz

    • ocpi.osp.n3xx.fsk_txrx_n310_cfg_1tx_1rx_dba_cnt_1tx_1rx_nocic_dba.hdl.0.n310.bitz

    • ocpi.osp.n3xx.fsk_loopback_n310_cfg_loopback_dba_cnt_loopback_nocic_dba.hdl.0.n310.bitz

    • ocpi.osp.n3xx.fsk_filerw_n310_base.hdl.0.n310.bitz

  2. Copy the OAS files and ACI program into the application working directory:

    • n310_fsk_tx.xml

    • n310_fsk_rx.xml

    • n310_fsk_txrx.xml

    • n310_fsk_loopback.xml

    • n310_fsk_filerw.xml

    • target-ettus_n310_v4/n310_fsk

  3. Make idata and odata directories within the application working directory:

% mkdir ./idata
% mkdir ./odata

  1. Copy the source file and filter coefficient files into idata directory (files are located in ./idata of n310_fsk application directory):

    • Os.jpeg

    • rx_rrcos_taps.dat

    • tx_rrcos_taps.dat

Execution

Copy and run the n310_fsk application script in the application working directory on the n310 platform:

% ./n310_fsk_app

FSK Applications
---------------------
[1] FSK_Tx
[2] FSK_Rx
[3] FSK_TxRx
[4] FSK_Loopback
[5] FSK_FileRW
--------------------------
Enter App Number:
3

Output

OCPI( 3:126.0832): drc_n310:
Daughterboard--DBA:
Power Off Reset Control
-----------------------
CHIP            | POR
-----------------------
CPLD Pathing    | x
LMK04828        | x
ADF4351         | x
DSA             | x
CPLD GPIO POR   | x
Transceiver Obj | x
-----------------------
OCPI( 3:127.0853): drc_n310: DBA lmkController: PLLs locked
OCPI( 3:127.0854): drc_n310: DBA lmkController: SYNC Event
OCPI( 3:127.0893): drc_n310: DBA Transceiver: rx_clkgen: MMCM-PLL locked
OCPI( 3:127.0913): drc_n310: DBA Transceiver: tx_clkgen: MMCM-PLL locked
OCPI( 3:128.0683): drc_n310: DBA Transceiver: MCS successful
OCPI( 3:128.0684): drc_n310: DBA Transceiver: CLKPLL locked
OCPI( 3:133.0395): drc_n310: DBA Transceiver: AD9371 ARM version 5.2.2
OCPI( 3:133.0613): drc_n310: DBA Transceiver: PLLs locked
OCPI( 3:133.0633): drc_n310: DBA Transceiver: waiting for initCals (or 60 second timer)
OCPI( 3:138.0575): drc_n310: DBA Transceiver: Calibrations completed successfully
OCPI( 3:138.0694): drc_n310: DBA Transceiver: tx_adxcvr: OK
OCPI( 3:138.0814): drc_n310: DBA Transceiver: rx_adxcvr: OK
OCPI( 3:138.0824): drc_n310: DBA Transceiver: rx_jesd status:
        Link is enabled
        Measured Link Clock: 48.000 MHz
        Reported Link Clock: 48.000 MHz
        Lane rate: 1920.000 MHz
        Lane rate / 40: 48.000 MHz
        Link status: DATA
        SYSREF captured: Yes
        SYSREF alignment error: No
OCPI( 3:138.0830): drc_n310: DBA Transceiver: rx_jesd lane 0 status:
Errors: 1
        CGS state: DATA
        Initial Frame Synchronization: Yes
        Lane Latency: 2 Multi-frames and 5 Octets
        Initial Lane Alignment Sequence: Yes
        DID: 0, BID: 0, LID: 0, L: 4, SCR: 1, F: 2
        K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
        FCHK: 0x47, CF: 0
        ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
        FC: 1920000 kHz
OCPI( 3:138.0836): drc_n310: DBA Transceiver: rx_jesd lane 1 status:
Errors: 1
        CGS state: DATA
        Initial Frame Synchronization: Yes
        Lane Latency: 2 Multi-frames and 27 Octets
        Initial Lane Alignment Sequence: Yes
        DID: 0, BID: 0, LID: 1, L: 4, SCR: 1, F: 2
        K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
        FCHK: 0x48, CF: 0
        ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
        FC: 1920000 kHz
OCPI( 3:138.0839): drc_n310: DBA Transceiver: rx_jesd lane 2 status:
Errors: 0
        CGS state: DATA
        Initial Frame Synchronization: Yes
        Lane Latency: 1 Multi-frames and 63 Octets
        Initial Lane Alignment Sequence: Yes
        DID: 0, BID: 0, LID: 2, L: 4, SCR: 1, F: 2
        K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
        FCHK: 0x49, CF: 0
        ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
        FC: 1920000 kHz
OCPI( 3:138.0842): drc_n310: DBA Transceiver: rx_jesd lane 3 status:
Errors: 1
        CGS state: DATA
        Initial Frame Synchronization: Yes
        Lane Latency: 2 Multi-frames and 1 Octets
        Initial Lane Alignment Sequence: Yes
        DID: 0, BID: 0, LID: 3, L: 4, SCR: 1, F: 2
        K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
        FCHK: 0x4A, CF: 0
        ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
        FC: 1920000 kHz
OCPI( 3:138.0954): drc_n310: DBA Transceiver: rx_adc: Successfully initialized
OCPI( 3:138.0955): drc_n310: DBA Transceiver: tx_jesd status:
        Link is enabled
        Measured Link Clock: 48.000 MHz
        Reported Link Clock: 48.000 MHz
        Lane rate: 1920.000 MHz
        Lane rate / 40: 48.000 MHz
        SYNC~: deasserted
        Link status: DATA
        SYSREF captured: Yes
        SYSREF alignment error: No
OCPI( 3:139.0064): drc_n310: DBA Transceiver: tx_dac: Successfully initialized
OCPI( 3:139.0065): drc_n310: DBA Transceiver: Successful configuration of ad9371 chip
OCPI( 3:139.0666): drc_n310: prepare_config():
Upgraded config 0 from inactive state to prepared
OCPI( 3:139.0668): drc_n310: update_tuning_frequency bypassed due to parameter remaining unchanged
OCPI( 3:139.0669): drc_n310: update_tuning_frequency bypassed due to parameter remaining unchanged
OCPI( 3:139.0784): drc_n310: start_config():
Upgraded config 0 from prepared state to OPERATING state

App runs for 5 seconds...

real_digitizer: sync pattern 0xFACE found

OCPI( 3:144.0834): drc_n310: stop_config():
Downgraded from operating state to PREPARED state
OCPI( 3:144.0843): drc_n310: DBA Transceiver: rx_jesd status:
        Link is disabled
        Measured Link Clock: 48.000 MHz
        Reported Link Clock: 48.000 MHz
        External reset is deasserted
OCPI( 3:144.0843): drc_n310: DBA Transceiver: tx_jesd status:
        Link is disabled
        Measured Link Clock: 48.000 MHz
        Reported Link Clock: 48.000 MHz
        External reset is deasserted
OCPI( 3:144.0844): drc_n310:
Daughterboard--DBA:
Power Off Reset Control
-----------------------
CHIP            | POR
-----------------------
CPLD Pathing    | x
LMK04828        | x
ADF4351         |
DSA             |
CPLD GPIO POR   | x
Transceiver Obj | x
-----------------------
OCPI( 3:144.0848): drc_n310:
Daughterboard--DBB: INACTIVE
Failed reset operation
OCPI( 3:144.0850): drc_n310: release_config():
Downgraded config 0 from prepared state to inactive state

App is Finished ....

OCPI( 3:144.0966): drc_n310:
Daughterboard--DBA:
Power Off Reset Control
-----------------------
CHIP            | POR
-----------------------
CPLD Pathing    |
LMK04828        |
ADF4351         |
DSA             |
CPLD GPIO POR   |
Transceiver Obj |
-----------------------
OCPI( 3:144.0967): drc_n310:
Daughterboard--DBB: INACTIVE
Failed reset operation
OCPI( 3:144.0967): drc_n310: release_config():
Downgraded config 0 from inactive state to inactive state

Verification

Verification of the output can be done using a image viewer application. For Linux systems, eog can used:

$ eog <n3100_fsk_app_artifact>.bin

The following application artifacts are generated within ./odata of the application working directory on the n310 platform:

  • n310_fsk_rx.bin

  • n310_fsk_txrx.bin

  • n310_fsk_loopback.bin

  • n310_fsk_filerw.bin

Troubleshooting

The application demonstrates inconsistent operation across runs, OAS implementations (n310_fsk_loopback.xml and n310_fsk_txrx.xml), and assembly builds. The most common issue is the corruption of the image header section. Using hexdump -C -n 100 <output_artifact>, the developer observed random bit errors when compared to the n310_fsk_filerw.xml application:

% hexdump -C -n 100 odata/n310_fsk_filerw.bin
00000000  ff d8 ff e0 00 10 4a 46  49 46 00 01 01 00 00 01  |......JFIF......|
00000010  00 01 00 00 ff db 00 84  00 09 06 06 14 12 11 15  |................|
00000020  14 12 14 16 15 15 15 18  17 18 19 16 15 18 1c 17  |................|
00000030  1a 16 17 1c 19 1a 18 15  1c 1c 1c 17 1c 26 20 1d  |.............& .|
00000040  19 25 1d 15 1b 1f 30 20  23 27 2a 2c 2c 2c 1b 1e  |.%....0 #'*,,,..|
00000050  31 35 30 2a 35 26 2c 2c  29 01 09 0a 0a 0e 0c 0e  |150*5&,,).......|
00000060  1a 0f 0f 1a                                       |....|

% hexdump -C -n 100 odata/n310_fsk_xxxxx.bin
00000000  ff d8 ff e0 00 10 4a 46  49 46 00 01 01 00 00 01  |......JFIF......|
00000010  00 01 00 00 df db 00 84  00 09 06 06 04 12 11 15  |................|
00000020  14 12 14 16 15 15 15 18  17 18 19 16 15 18 1c 17  |................|
00000030  1a 16 17 1c 19 1a 18 15  1c 1c 1c 17 1c 26 20 1d  |.............& .|
00000040  19 25 1d 14 1b 1f 30 20  23 27 2a 2c 2c 2c 1a 1e  |.%....0 #'*,,,..|
00000050  31 35 30 2a 35 26 28 2c  29 01 09 0a 0a 0e 0c 0e  |150*5&(,).......|
00000060  1a 0f 0f 1a                                       |....|

In addition, the developer recommends ensuring the bit file is reloaded by the OpenCPI framework by not running the exact OAS implementation of the application consecutively. To ensure the framework reloads the bit file, please run another implementation. We have observed inconsistent operations detecting the SYN pattern when running the exact implementation consecutively.