exp_us HDL Worker
Pipelined HDL implementation of exponentiation, allowing one input and one output every FPGA clock cycle, with a delay of 36 clock cycles through the pipeline.
Detail
The input scaling factor \(N\) can be set anywhere from 0 to 16 without any loss being introduced by the HDL implementation. As the exponentiation primitive is designed for UQ16.16 fixed point input values and UQ16.16 fixed point output values. With the output of the exponentiation primitive passed to a rounding half-up primitive instance where the output value is rounded to the nearest integer (0.5 rounded up) and the 16 fractional bits thrown away.
Worker Properties
ocpi_buffer_size_outputType:
ushortAccess:
Parameter:
FalseWritable:
FalseInitial:
TrueVolatile:
FalseRead back:
False
Default value:
0
ocpi_blocked_outputType:
ulongAccess:
Parameter:
FalseWritable:
FalseInitial:
FalseVolatile:
TrueRead back:
False
Default value:
None
ocpi_max_latency_outputType:
ushortAccess:
Parameter:
TrueWritable:
FalseInitial:
FalseVolatile:
FalseRead back:
False
Default value:
None
ocpi_latency_outputType:
ushortAccess:
Parameter:
FalseWritable:
FalseInitial:
FalseVolatile:
TrueRead back:
False
Default value:
None
ocpi_messages_outputType:
ulongAccess:
Parameter:
FalseWritable:
FalseInitial:
FalseVolatile:
TrueRead back:
False
Default value:
None
ocpi_bytes_outputType:
ulongAccess:
Parameter:
FalseWritable:
FalseInitial:
FalseVolatile:
TrueRead back:
False
Default value:
None
Worker Ports
inputProtocol:
ushort_timed_sampleOptional:
False
outputProtocol:
ushort_timed_sampleOptional:
False
Inputs:
Outputs:
Utilisation
Utilization reporting is not currently implemented.