Adder (`adder_s`)

Adds together, or finds the difference between, two input values.

Design

Adds together two input values, with the option to negate either input before the addition.

The mathematical representation of the implementation is given in (80).

(80)\[z[n] = (x[n] * N_x) + (y[n] * N_y)\]

\(x[n]\) and \(y[n]\) are the input values.

\(N_x\) and \(N_y\) are the negate_input_1 and negate_input_2 properties, which have the value 1 when their respective property is False and -1 when their respective property is True.

\(z[n]\) is the output values.

A block diagram representation of the implementation is given in Figure 128:.

Block diagram outlining adder implementation. — Figure 128: Adder implementation.

Interface

<?xml version="1.0"?>
<componentspec>
  <property name="negate_input_1" type="bool" writable="true" default="false" description="When set to true input_1 will be negated before the addition. When false, input_1 will be used by the adder directly."/>
  <property name="negate_input_2" type="bool" writable="true" default="false" description="When set to true input_2 will be negated before the addition. When false, input_2 will be used by the adder directly."/>
  <port name="input_1" producer="false" protocol="short_timed_sample-prot"/>
  <port name="input_2" producer="false" protocol="short_timed_sample-prot"/>
  <port name="output" producer="true" protocol="short_timed_sample-prot"/>
</componentspec>

Ports

Inputs:

input_1: Input samples port.
- Protocol: short_timed_sample-prot
- Optional: False
input_2: Input samples port.
- Protocol: short_timed_sample-prot
- Optional: False

Outputs:

output: Primary output samples port.
- Protocol: short_timed_sample-prot
- Optional: False

Opcode Handling

Addition is only applied to data in sample opcode messages. All other opcode messages received on input_1 are passed through this component without any effect. All messages with a non-sample opcode received on input_2 are discarded.

Sample message lengths received on input_1 are persevered on the output. Sample message lengths received on input_2 are ignored.

Properties

negate_input_1: When set to true input_1 will be negated before the addition. When false, input_1 will be used by the adder directly.
- Type: bool
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: False
- Default value: false
negate_input_2: When set to true input_2 will be negated before the addition. When false, input_2 will be used by the adder directly.
- Type: bool
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: False
- Default value: false

Implementations

adder_s (HDL)
adder_s (RCC)

Example Application

<?xml version="1.0"?>
<application done="file_write">
  <instance component="ocpi.core.file_read" connect="adder_s" to="input_1">
    <property name="filename" value="input_1.bin"/>
  </instance>
  <instance component="ocpi.core.file_read" connect="adder_s" to="input_2">
    <property name="filename" value="input_2.bin"/>
  </instance>
  <instance component="ocpi.comp.sdr.math.adder_s" connect="file_write">
    <property name="negate_input_1" value="false"/>
    <property name="negate_input_2" value="false"/>
  </instance>
  <instance component="ocpi.core.file_write">
    <property name="filename" value="output.bin"/>
  </instance>
</application>

Dependencies

The dependencies to other elements in OpenCPI are:

None

There is also a dependency on:

ieee.std_logic_1164

ieee.numeric_std

Limitations

Limitations of adder_s are:

None.

Testing

Tested platforms: None

Component testing not completed.

Adder (adder_s)