Timegate (`timegate`)

Timed transmit of complex IQ data using complex time sampled protocol. timegate_csts is an asset in the ocpi.assets.util_comps component library. Implementations include the timegate_csts HDL Worker (timegate_csts.hdl). Tested platforms include xsim, modelsim, zed, e3xx.

Function

Inputs complex short time sampled data and outputs complex short time sample data when the current time exceeds the gated time.

Current time is provided as an input to the component on the time interface. The time gated timestamp is a 96-bit number with the first 32 bits corresponding to seconds and the last 40 bits corresponding to fractional seconds. The default state of the the timegate is open, which means data samples flow between the input and the output ports.

When a timestamp opcode is received on the input port that is greater than the current time, the timegate component stops consuming data from the input port. When the current time exceeds the timestamp, the gate is open and starts passing samples through the component.

The time interface from which the current time is derived originates from the OpenCPI time server, which is instanced as part of the platform worker. Furthermore, an additional component (time client) is dynamically instanced by the framework for all components that declare time interfaces. The time client communicates with the time server and produces the time interface seen by the component.

Interface

<ComponentSpec>

  <Property name='ignore_time_stamps'
            type='bool'
            initial='true'
            default='false'
            description='Ignores/drops timestamps, disabling the timegating functionality.'/>
  <Property name='time_correction'
            type='ulong'
            writable='true'
            default='0'
            description='unsigned fixed point fraction of second which is subtracted from
            the applied time to open the gate early so that the actual RF transmission happens at
	          the right time'/>
  <Property name='late_time_sticky'
            type='bool'
            volatile='true'
            description='Timestamp (corrected) arrived too late - after the indicated time'/>
  <Property name='clr_late_time_sticky'
            type='bool'
            writable='true'
            default='false'
            description='Writing a value of true clears
            correction_overflow_sticky.'/>
  <Property name='force_error_on_invalid_time_at_start'
            type='bool'
            initial='true'
            default='false'
            description='Forces worker into the unusable state if the time
            invalid signal is low during the worker initialized state.'/>
  <Property name='actual_time_to_requested_time_delta' 
            type="uLongLong"  
            Volatile='true' 
            description='Delta between the actual time transmitted (when the gate opens 
            to allow samples through) to the requested timestamp (corrected).'/>

  <Port name='in' producer='false' protocol='complex_short_timed_sample-prot'/>
  <Port name='out' producer='true' protocol='complex_short_timed_sample-prot'/>

</ComponentSpec>

Properties

ignore_time_stamps: Ignores/drops timestamps, disabling the timegating functionality.
- Type: bool
- Access:
  - Parameter: False
  - Writable: False
  - Initial: True
  - Volatile: False
- Default value: false
time_correction: unsigned fixed point fraction of second which is subtracted from the applied time to open the gate early so that the actual RF transmission happens at the right time.
- Type: ulong
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: False
- Default value: 0
late_time_sticky: Timestamp (corrected) arrived too late - after the indicated time.
- Type: bool
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None
clr_late_time_sticky: Writing a value of true clears correction_overflow_sticky.
- Type: bool
- Access:
  - Parameter: False
  - Writable: True
  - Initial: False
  - Volatile: False
- Default value: false
force_error_on_invalid_time_at_start: Forces worker into the unusable state if the time invalid signal is low during the worker initialized state.
- Type: bool
- Access:
  - Parameter: False
  - Writable: False
  - Initial: True
  - Volatile: False
- Default value: false
actual_time_to_requested_time_delta: Delta between the actual time transmitted (when the gate opens to allow samples through) to the requested timestamp (corrected).
- Type: ulonglong
- Access:
  - Parameter: False
  - Writable: False
  - Initial: False
  - Volatile: True
- Default value: None

Ports

Inputs:

in: Signed complex samples with timestamps.
- Protocol: complex_short_timed_sample-prot
- Optional: False

Outputs:

out: Signed complex samples.
- Protocol: complex_short_timed_sample-prot
- Optional: False

Implementations

timegate_csts (HDL)

Example Application

<?xml version="1.0"?>
<application done="file_write">
  <instance component="ocpi.core.file_read" connect="timestamper">
    <property name="filename" value="input.bin"/>
  </instance>
  <instance component="ocpi.assets.util_comps.timegate_csts" connect="file_write">
  </instance>
  <instance component="ocpi.core.file_write">
    <property name="filename" value="output.bin"/>
  </instance>
</application>

Dependencies

The dependencies to other elements in OpenCPI are:

None.

Limitations

Limitations of timegate_csts are:

The time client only provides a 64-bit interface, thus some of the fractional time (40 bits) from the timestamp gets truncated.

Testing

One test case is implemented to validate the timegate_csts component:

The input file contains one timestamp and 8 notional complex data samples. The timestamp is zero seconds and fractional second is set to max value (0xFFFFFFFFFF). For verification, the timegate_csts passes the complex data samples through the gate.

Tested platforms: None

Component testing not completed.

Timegate (timegate)