timestamper HDL Worker

Application worker HDL implementation with a settable runtime configuration parameter for the enable property.

Detail

Worker Properties

  • enable

    • Type: bool

    • Access:

      • Parameter: False

      • Writable: False

      • Initial: True

      • Volatile: False

      • Read back: False

    • Default value: true

Worker Ports

    Inputs:

  • in: Signed complex samples.

    • Type: streaminterface

    • Data width: 32

    • Number of opcodes: 256

    • Protocol: iqstream_protocol.xml

    • Optional: False

    • Outputs:

  • out: Signed complex samples.

    • Type: streaminterface

    • Data width: 32

    • Number of opcodes: 256

    • Protocol: iqstream_with_sync_protocol.xml

    • Optional: False

    • Time:

  • time: Time interface provided by OpenCPI time server.

    • Type: timeinterface

    • Seconds width: 32

    • Fraction width: 32

Control Timing and Signals

The timestamper HDL worker uses the clock from the control plane and standard control signals.

Data presented on the input appears on the output clock three cycles later (latency=3). Two of the three clock cycles consist of a time message.

Utilization

Utilization reporting is not currently implemented.