https://forums.xilinx.com/t5/Design-Entry/What-to-expect-when-using-edf-files-compiled-for-Artix-7-in-a/m-p/1238396#M26610
The link above is post on the Xilinx forum that posses the question of what to expect when using EDF files built for A7 (HdlTarget=zynq) in a design which is actually targeting a K7, which represents the current situation when building for a PicoZed 7030 platform.
I propose creating a new HdlTarget “zynq_k7†and properly assigning the 7-series devices across '“zynq†(A7) and “zynq_k7†(K7). The following are the proposed changes to hdl-targets.mk:
\+HdlTargets_xilinx:=isim virtex5 virtex6 spartan3adsp spartan6 zynq_ise zynq zynq_k7 zynq_ultra xsim x4sim\
\-HdlTargets_zynq:=xc7z007s xc7z012s xc7z014s xc7z010 xc7z015 xc7z020 xc7z030 xc7z035 xc7z045 xc7z100 xc7z035i\
\+HdlTargets_zynq:=xc7z007s xc7z012s xc7z014s xc7z010 xc7z015 xc7z020\
\+HdlTargets_zynq_k7:=xc7z030 xc7z035 xc7z045 xc7z100 xc7z035i\
\+HdlDefaultTarget_zynq_k7:=xc7z030\
\+HdlToolSet_zynq_k7:=vivado
Thoughts?
Received on Fri May 07 2021 - 11:56:20 CDT