Re: [Discuss OpenCPI] Vivado Multiple Instantiation Debug Cores
On Tue, Aug 4, 2020 at 4:22 PM Jerry Darko <jerry.darko_at_cnftech.com> wrote:
>
>
> ------------------------------
> *From:* Brian Padalino <bpadalino_at_gmail.com>
> *Sent:* Tuesday, August 4, 2020 4:03 PM
> *To:* Jerry Darko <jerry.darko_at_cnftech.com>
> *Cc:* discuss_at_lists.opencpi.org <discuss_at_lists.opencpi.org>
> *Subject:* Re: [Discuss OpenCPI] Vivado Multiple Instantiation Debug Cores
>
> On Tue, Aug 4, 2020 at 3:53 PM Jerry Darko <jerry.darko_at_cnftech.com>
> wrote:
>
> Davis and I have run into this. One way around it is to open up the
> container or assembly .edif (sorry I forget which one at the moment) and
> then use the write_debug_probes command to generate the .ltx file and use
> that .ltx file instead.
>
>
> My failure is at placement of the assembly, not at the debug time which I
> think is where the ltx file would come into play.
>
> Are you able to get through and place your design successfully with
> multiple EDIF netlists instrumented for debug?
>
> Sorry I misread. Some months back I was debugging some framework
> infrastructure such as the wsi_width_clock_adapters and a design had
> multiple of them and it was able to place the design successfully.
>
> Can you please post the error message?
>
I am placing the ILA in the ad9361_adc_sub on:
dev_data_ch0_out_out[adc_data_I]
dev_data_ch0_out_out[adc_data_Q]
dev_data_ch1_out_out[adc_data_I]
dev_data_ch1_out_out[adc_data_Q]
And there are two instances of that device.
During placing, I get this error:
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
ERROR: [Place 30-174] Unroutable Placement! The following clock source
components are placed too far from each other. These clocks drive common
load instances. This requires them to be placed in a relative way such that
both clocks can drive the common load instances. Please refer to the
clocking user guide for more details on which clock regions these clock
sources can drive.
ftop/pfconfig_i/afe0_adc_sub_i/worker/clk_in_lvds.BUFR_inst (BUFR.O) is
provisionally placed by clockplacer on BUFR_X1Y7
ftop/pfconfig_i/afe1_adc_sub_i/worker/clk_in_lvds.BUFR_inst (BUFR.O) is
provisionally placed by clockplacer on BUFR_X1Y11
ftop/pfconfig_i/afe0_adc_sub_i/u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram
(RAMB18E1.CLKARDCLK) cannot be placed
ftop/pfconfig_i/afe0_adc_sub_i/u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram
(RAMB18E1.CLKBWRCLK) cannot be placed
ftop/pfconfig_i/afe0_adc_sub_i/u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(RAMB36E1.CLKARDCLK) cannot be placed
ftop/pfconfig_i/afe0_adc_sub_i/u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(RAMB36E1.CLKBWRCLK) cannot be placed
ftop/pfconfig_i/afe0_adc_sub_i/u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(RAMB36E1.CLKARDCLK) cannot be placed
ftop/pfconfig_i/afe0_adc_sub_i/u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(RAMB36E1.CLKBWRCLK) cannot be placed
ftop/pfconfig_i/afe0_adc_sub_i/u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(RAMB36E1.CLKARDCLK) cannot be placed
ftop/pfconfig_i/afe0_adc_sub_i/u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(RAMB36E1.CLKBWRCLK) cannot be placed
ftop/pfconfig_i/afe0_adc_sub_i/u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(RAMB36E1.CLKARDCLK) cannot be placed
ftop/pfconfig_i/afe0_adc_sub_i/u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(RAMB36E1.CLKBWRCLK) cannot be placed
ftop/pfconfig_i/afe0_adc_sub_i/u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(RAMB36E1.CLKARDCLK) cannot be placed
ftop/pfconfig_i/afe0_adc_sub_i/u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(RAMB36E1.CLKBWRCLK) cannot be placed
Following this, there is a statement about the clocks associated with this:
The above error could possibly be related to other connected instances.
Following is a list of
all the related clock rules and their respective instances.
Clock Rule: rule_bufh_bufr_ramb
Status: PASS
Rule Description: Reginal buffers in the same clock region must drive a
total number of brams less
than the capacity of the region
ftop/pfconfig_i/afe0_adc_sub_i/worker/clk_in_lvds.BUFR_inst (BUFR.O) is
provisionally placed by clockplacer on BUFR_X1Y7
Clock Rule: rule_bufr_IoClkLds
Status: PASS
Rule Description: A BUFR driving any number of IOBs must be placed within
the same clock region
ftop/pfconfig_i/afe0_adc_sub_i/worker/clk_in_lvds.BUFR_inst (BUFR.O) is
provisionally placed by clockplacer on BUFR_X1Y7
ftop/pfconfig_i/afe0_adc_sub_i/worker/supported_so_far.buf_data_loop[0].data_ddr
(IDDR.C) is locked to ILOGIC_X1Y92
ftop/pfconfig_i/afe0_adc_sub_i/worker/supported_so_far.buf_data_loop[1].data_ddr
(IDDR.C) is locked to ILOGIC_X1Y88
ftop/pfconfig_i/afe0_adc_sub_i/worker/supported_so_far.buf_data_loop[2].data_ddr
(IDDR.C) is locked to ILOGIC_X1Y84
ftop/pfconfig_i/afe0_adc_sub_i/worker/supported_so_far.buf_data_loop[3].data_ddr
(IDDR.C) is locked to ILOGIC_X1Y90
ftop/pfconfig_i/afe0_adc_sub_i/worker/supported_so_far.buf_data_loop[4].data_ddr
(IDDR.C) is locked to ILOGIC_X1Y86
ftop/pfconfig_i/afe0_adc_sub_i/worker/supported_so_far.buf_data_loop[5].data_ddr
(IDDR.C) is locked to ILOGIC_X1Y82
ftop/pfconfig_i/afe0_adc_sub_i/worker/supported_so_far.rx_frame_p_ddr
(IDDR.C) is locked to ILOGIC_X1Y74
Clock Rule: rule_iotile_bufr
Status: PASS
Rule Description: An IO driving a BUFR must both be placed in the same
clock region
ftop/pfconfig_i/afe0_data_sub_i/worker/mode7.data_clk/UNSPECIFIED_gen.differential_prim.buf_generic.buf
(IBUFDS.O) is locked to IOB_X1Y76
ftop/pfconfig_i/afe0_adc_sub_i/worker/clk_in_lvds.BUFR_inst (BUFR.I) is
provisionally placed by clockplacer on BUFR_X1Y7
Clock Rule: rule_bufh_bufr_ramb
Status: PASS
Rule Description: Reginal buffers in the same clock region must drive a
total number of brams less
than the capacity of the region
ftop/pfconfig_i/afe1_adc_sub_i/worker/clk_in_lvds.BUFR_inst (BUFR.O) is
provisionally placed by clockplacer on BUFR_X1Y11
Clock Rule: rule_bufr_IoClkLds
Status: PASS
Rule Description: A BUFR driving any number of IOBs must be placed within
the same clock region
ftop/pfconfig_i/afe1_adc_sub_i/worker/clk_in_lvds.BUFR_inst (BUFR.O) is
provisionally placed by clockplacer on BUFR_X1Y11
ftop/pfconfig_i/afe1_adc_sub_i/worker/supported_so_far.buf_data_loop[0].data_ddr
(IDDR.C) is locked to ILOGIC_X1Y142
ftop/pfconfig_i/afe1_adc_sub_i/worker/supported_so_far.buf_data_loop[1].data_ddr
(IDDR.C) is locked to ILOGIC_X1Y138
ftop/pfconfig_i/afe1_adc_sub_i/worker/supported_so_far.buf_data_loop[2].data_ddr
(IDDR.C) is locked to ILOGIC_X1Y134
ftop/pfconfig_i/afe1_adc_sub_i/worker/supported_so_far.buf_data_loop[3].data_ddr
(IDDR.C) is provisionally placed by clockplacer on ILOGIC_X1Y132
ftop/pfconfig_i/afe1_adc_sub_i/worker/supported_so_far.buf_data_loop[4].data_ddr
(IDDR.C) is provisionally placed by clockplacer on ILOGIC_X1Y136
ftop/pfconfig_i/afe1_adc_sub_i/worker/supported_so_far.buf_data_loop[5].data_ddr
(IDDR.C) is provisionally placed by clockplacer on ILOGIC_X1Y140
ftop/pfconfig_i/afe1_adc_sub_i/worker/supported_so_far.rx_frame_p_ddr
(IDDR.C) is locked to ILOGIC_X1Y124
Clock Rule: rule_iotile_bufr
Status: PASS
Rule Description: An IO driving a BUFR must both be placed in the same
clock region
ftop/pfconfig_i/afe1_data_sub_i/worker/mode7.data_clk/UNSPECIFIED_gen.differential_prim.buf_generic.buf
(IBUFDS.O) is locked to IOB_X1Y126
ftop/pfconfig_i/afe1_adc_sub_i/worker/clk_in_lvds.BUFR_inst (BUFR.I) is
provisionally placed by clockplacer on BUFR_X1Y11
If I open the xpr and try the implementation, the following warning stands
out to me:
[Shape Builder 18-119] Failed to create BSCAN shape for instance
ftop/pfconfig_i/afe1_adc_sub_i/dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst.
Found overlapping instances within the shape:
ftop/pfconfig_i/afe1_adc_sub_i/dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst
and
ftop/pfconfig_i/afe0_adc_sub_i/dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst.
It's just a critical warning, but it seems potentially problematic. Later
on there are also some warnings regarding a file called
xsdbm_cc_late_late.xdc complaining about no such variables.
Any help or insight would be very helpful.
Thanks,
Brian
>
Received on Tue Aug 04 2020 - 21:45:33 CDT
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