Re: [Discuss OpenCPI] Vivado Multiple Instantiation Debug Cores

From: Jerry Darko <jerry.darko_at_cnftech.com>
Date: Tue, 04 Aug 20 20:22:40 +0000

________________________________
From: Brian Padalino <bpadalino_at_gmail.com>
Sent: Tuesday, August 4, 2020 4:03 PM
To: Jerry Darko <jerry.darko_at_cnftech.com>
Cc: discuss_at_lists.opencpi.org <discuss_at_lists.opencpi.org>
Subject: Re: [Discuss OpenCPI] Vivado Multiple Instantiation Debug Cores

On Tue, Aug 4, 2020 at 3:53 PM Jerry Darko <jerry.darko_at_cnftech.com<mailto:jerry.darko_at_cnftech.com>> wrote:
Davis and I have run into this. One way around it is to open up the container or assembly .edif (sorry I forget which one at the moment) and then use the write_debug_probes command to generate the .ltx file and use that .ltx file instead.

My failure is at placement of the assembly, not at the debug time which I think is where the ltx file would come into play.

Are you able to get through and place your design successfully with multiple EDIF netlists instrumented for debug?
Sorry I misread. Some months back I was debugging some framework infrastructure such as the wsi_width_clock_adapters and a design had multiple of them and it was able to place the design successfully.

Can you please post the error message?

Thanks,
Brian


Received on Tue Aug 04 2020 - 20:22:40 CDT