n310_cpld_spi HDL Worker

Detail

HDL implementation of n310_cpld_spi device worker in support of the n310 platform.

Worker Properties

  • VIVADO_ILA_p: Build-time parameter for Xilinx Integrated Logic Analyzer (ILA).

    • Type: bool

    • Access:

      • Parameter: True

      • Writable: False

      • Initial: False

      • Volatile: False

      • Read back: False

    • Default value: None

Worker Signals

  • DBA_CPLD_PS_SCLK

    • Direction: out

    • Differential: false

    • Pin: false

  • DBA_CPLD_PS_SDO

    • Direction: out

    • Differential: false

    • Pin: false

  • DBA_CPLD_PS_SDI

    • Direction: in

    • Differential: false

    • Pin: false

  • DBA_CPLD_PL_SCLK

    • Direction: out

    • Differential: false

    • Pin: false

  • DBA_CPLD_PL_SDO

    • Direction: out

    • Differential: false

    • Pin: false

  • DBA_CPLD_PL_SDI

    • Direction: in

    • Differential: false

    • Pin: false

  • DBB_CPLD_PS_SCLK

    • Direction: out

    • Differential: false

    • Pin: false

  • DBB_CPLD_PS_SDO

    • Direction: out

    • Differential: false

    • Pin: false

  • DBB_CPLD_PS_SDI

    • Direction: in

    • Differential: false

    • Pin: false

  • DBB_CPLD_PL_SCLK

    • Direction: out

    • Differential: false

    • Pin: false

  • DBB_CPLD_PL_SDO

    • Direction: out

    • Differential: false

    • Pin: false

  • DBB_CPLD_PL_SDI

    • Direction: in

    • Differential: false

    • Pin: false

  • DBA_CPLD_PS_CSB

    • Direction: out

    • Differential: false

    • Pin: false

  • DBA_LMK_PS_CSB

    • Direction: out

    • Differential: false

    • Pin: false

  • DBA_DAC_PS_CSB

    • Direction: out

    • Differential: false

    • Pin: false

  • DBA_CPLD_PL_CSB

    • Direction: out

    • Differential: false

    • Pin: false

  • DBA_TXLO_PL_CSB

    • Direction: out

    • Differential: false

    • Pin: false

  • DBA_RXLO_PL_CSB

    • Direction: out

    • Differential: false

    • Pin: false

  • DBB_CPLD_PS_CSB

    • Direction: out

    • Differential: false

    • Pin: false

  • DBB_LMK_PS_CSB

    • Direction: out

    • Differential: false

    • Pin: false

  • DBB_DAC_PS_CSB

    • Direction: out

    • Differential: false

    • Pin: false

  • DBB_CPLD_PL_CSB

    • Direction: out

    • Differential: false

    • Pin: false

  • DBB_TXLO_PL_CSB

    • Direction: out

    • Differential: false

    • Pin: false

  • DBB_RXLO_PL_CSB

    • Direction: out

    • Differential: false

    • Pin: false

Signal Ports

  <!--Daughterboard A Signals -->
  <Signal Output="DBA_CPLD_PS_SCLK"/>
  <Signal Output="DBA_CPLD_PS_SDO"/>  
  <Signal Input= "DBA_CPLD_PS_SDI"/>
  <Signal Output="DBA_CPLD_PL_SCLK"/>
  <Signal Output="DBA_CPLD_PL_SDO"/> 
  <Signal Input= "DBA_CPLD_PL_SDI"/>  
  
  <!--Daughterboard B Signals -->
  <Signal Output="DBB_CPLD_PS_SCLK"/>
  <Signal Output="DBB_CPLD_PS_SDO"/>  
  <Signal Input= "DBB_CPLD_PS_SDI"/>
  <Signal Output="DBB_CPLD_PL_SCLK"/>
  <Signal Output="DBB_CPLD_PL_SDO"/> 
  <Signal Input= "DBB_CPLD_PL_SDI"/>

  <!--Daughterboard Chip Selection Signals -->
  <Signal Output="DBA_CPLD_PS_CSB"/>
  <Signal Output="DBA_LMK_PS_CSB"/>
  <Signal Output="DBA_DAC_PS_CSB"/>
  <Signal Output="DBA_CPLD_PL_CSB"/> 
  <Signal Output="DBA_TXLO_PL_CSB"/> 
  <Signal Output="DBA_RXLO_PL_CSB"/>
    
  <Signal Output="DBB_CPLD_PS_CSB"/>
  <Signal Output="DBB_LMK_PS_CSB"/>
  <Signal Output="DBB_DAC_PS_CSB"/>
  <Signal Output="DBB_CPLD_PL_CSB"/>
  <Signal Output="DBB_TXLO_PL_CSB"/>
  <Signal Output="DBB_RXLO_PL_CSB"/>