metadata_stressor HDL Worker

Application worker HDL implementation with a settable runtime configuration parameter for component port data width.

Detail

The metadata stressor HDL worker has four modes that control its primary operation: bypass, data, metadata, and full. The mode property is used to establish the mode.

In bypass mode, the HDL worker passes through the data and metadata it receives without change.

In data mode, the HDL worker passes through the metadata associated with a message unchanged, but the data will be withheld based on the duty cycle or lfsr, imitating data starvation for the unit under test. (If the enable_take_lsfr property is not set to true or the take_duty property is not set to greater than 1, the worker will set the duty cycle to 5.)

In metadata mode, the HDL worker passes through the data (not intentionally withholding any data) but manipulates the metadata in the following ways:

• Early start of message (SOM), data, late end of message (EOM)

• Early SOM, data, EOM with data

• SOM with data, data, late EOM

• SOM with data, data, EOM with data, (single-word message if that is what is received)

• Zero-length message (if the allow_zlms property is true)

It repeats those patterns so long as there is data.

In full mode, the HDL worker combines data and metadata modes, manipulating both the metadata and starving the unit under test of data. Do not use data mode and the allow_zlms property in combination. Data mode does not allow for manipulation of metadata, so zero-length messages cannot be inserted. Enabling both does not cause a failure, but one behavior will preclude the expression of the other.

The following figure shows a block diagram representation of the HDL implementation:

Figure 6: Metadata Stressor HDL Worker Block Diagram

Worker Properties

• DATA_WIDTH_p

  • Type: ulong

  • Access:

    • Parameter: True

    • Writable: False

    • Initial: False

    • Volatile: False

    • Read back: False

  • Default value: None

• ocpi_buffer_size_out

  • Type: ushort

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: True

    • Volatile: False

    • Read back: False

  • Default value: 0

• ocpi_blocked_out

  • Type: ulong

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• ocpi_max_latency_out

  • Type: ushort

  • Access:

    • Parameter: True

    • Writable: False

    • Initial: False

    • Volatile: False

    • Read back: False

  • Default value: None

• ocpi_latency_out

  • Type: ushort

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• ocpi_messages_out

  • Type: ulong

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• ocpi_bytes_out

  • Type: ulong

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

Worker Ports

Inputs:

• in: Size defined by DATA_WIDTH_p.

  • Protocol: None

  • Optional: False

Outputs:

• out: Size defined by DATA_WIDTH_p.

  • Protocol: None

  • Optional: False

Finite State Machine

The following figure shows an abbreviated representation of the primary finite state machine implemented in the HDL version of the metadata stressor component.

Figure 7: Metadata Stressor HDL Worker Finite State Machine

Control Timing and Signals

The metadata stressor HDL worker implementation uses the clock from the control plane and standard control plane signals.