n310 Platform Worker

The Ettus Research N310 USRP platform is a high-performance Software-Defined Radio (SDR) platform for wireless applications. The architecture consists of a Xilinx Zynq-7100 System-on-Chip (SoC) motherboard with dual AD9371 transceiver daughterboards to provide multiple-channel deployment. The Processing System (PS) is a dual-core ARM Cortex-A9 800-MHZ CPU running OpenEmbedded Linux, and the Programmable Logic (PL) is a Kintex Series-7 FPGA.

• Max Channels: 4 Tx, 4 Rx Channels

• Frequency Range: 10 MHz to 6 GHz

• Channel Bandwidth: up to 70 MHz @ 10 MHz steps (100 MHz - future release)

• Gain Control: up to 30 dB @ 0.5 dB steps

• OpenCPI Control Plane Clock: 100 MHz (166.67 MHz - future release)

• Master Clock Rates (MCR): 90 and 96 MSps (122.88, 125, and 153.6 MSps - future release)

• Operational Modes: Embedded (Networked - future release)

Figure 29: Single Daugtherboard Architecture Diagram

Figure 30: Dual Daugtherboard Architecture Diagram

Control Plane Device Workers

• drc_n310: OpenCPI Digital Radio Controller (DRC)

• n310_cpld_spi: SPI interface to the Master CPLD Controller

• n310_gpio: Control interface for the Master CPLD Controller

• n310_dsa: Control interface for the N310 Digital Step Attenuators (DSA)

• ad9371_spi: SPI interface Analog Devices (ADI) AD9371 Transceiver

• ad9371_gpio: GPIO debugging interface for the Analog Devices (ADI) AD9371 Transceiver

• jesd_raw2axi_interface: OpenCPI RAW properties to AXI registers for the Analog Devices (ADI) JESD204B Framework cores

Data Plane Device Workers

• adrv9371_jesd_2tx_2rx: JESD204B Interface

• data_sink_qdac_ad9371_sub: JESD204B qDAC Subdevice Worker

• data_src_qadc_ad9371_sub: JESD204B qADC Subdevice Worker

• n310_qdac_csts: N310 qDAC Class Worker

• n310_qadc_csts: N310 qADC Class Worker

• cic_dec_csts: Cascaded Integrator-Comb (CIC) Filter Worker - Decimation

• cic_int_csts: Cascaded Integrator-Comb (CIC) Filter Worker - Interpolation

Detail

Worker Properties

• sdp_channels: Number of OpenCPI Scalable Data Plane (SDP) Interfaces connected to the Xilinx Zynq High-Performance AXI Ports.

  • Type: ulong

  • Access:

    • Parameter: True

    • Writable: False

    • Initial: False

    • Volatile: False

    • Read back: False

  • Default value: None

• sdpDropCount: Number of SDP Packet Dropped.

  • Type: uchar

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• useFCLK: Build-time parameter to select the Xilinx Zynq FCLK (0-3) to used for OpenCPI Control Plane Clock.

  • Type: uchar

  • Access:

    • Parameter: True

    • Writable: False

    • Initial: False

    • Volatile: False

    • Read back: False

  • Default value: None

Worker Signals

• FPGA_PUDC_B

  • Direction: in

  • Differential: false

  • Pin: true