jesd_raw2axi_interface HDL Worker

Detail

HDL implementation of jesd_raw2axi_interface device worker in support of the n310 platform. This device worker maps RAW properties to AXI registers for the Analog Device JESD204B Framework cores implemented within the adrv9371_jesd_2tx_2rx device worker.

Worker Properties

• max_addr: Max address in the register map for raw properties.

  • Type: ushort

  • Access:

    • Parameter: True

    • Writable: False

    • Initial: False

    • Volatile: False

    • Read back: False

  • Default value: None

• tpl_tx_raw: Raw property interface for the JESD Tx Transport Layer.

  • Type: ulong

    • Array dimensions: ['320']

  • Access:

    • Parameter: False

    • Writable: True

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• link_tx_raw: Raw property interface for the JESD Tx Link Layer.

  • Type: ulong

    • Array dimensions: ['320']

  • Access:

    • Parameter: False

    • Writable: True

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• tpl_rx_raw: Raw property interface for the JESD Rx Transport Layer.

  • Type: ulong

    • Array dimensions: ['320']

  • Access:

    • Parameter: False

    • Writable: True

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• link_rx_raw: Raw property interface for the JESD Rx Link Layer.

  • Type: ulong

    • Array dimensions: ['320']

  • Access:

    • Parameter: False

    • Writable: True

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• clk_rx_raw: Raw property interface for the JESD Rx Clock Generator.

  • Type: ulong

    • Array dimensions: ['320']

  • Access:

    • Parameter: False

    • Writable: True

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• clk_tx_raw: Raw property interface for the JESD Tx Clock Generator.

  • Type: ulong

    • Array dimensions: ['320']

  • Access:

    • Parameter: False

    • Writable: True

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• phy_rx_raw: Raw property interface for the JESD Rx Physical Layer.

  • Type: ulong

    • Array dimensions: ['320']

  • Access:

    • Parameter: False

    • Writable: True

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• phy_tx_raw: Raw property interface for the JESD Tx Physical Layer.

  • Type: ulong

    • Array dimensions: ['320']

  • Access:

    • Parameter: False

    • Writable: True

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

Worker Ports

Interfaces (other than data I/O ports):

• tx_event: Transmitter Event Trigger.

  • Type: devsignal

• clk_rx_axi: AXI-Lite Interface for JESD Rx Clock Generator.

  • Type: devsignal

• clk_tx_axi: AXI-Lite Interface for JESD Tx Clock Generator.

  • Type: devsignal

• tpl_tx_axi: AXI-Lite Interface for JESD Tx Transport Layer.

  • Type: devsignal

• tpl_rx_axi: AXI-Lite Interface for JESD Rx Transport Layer.

  • Type: devsignal

• link_tx_axi: AXI-Lite Interface for JESD Tx Link Layer.

  • Type: devsignal

• link_rx_axi: AXI-Lite Interface for JESD Rx Link Layer.

  • Type: devsignal

• phy_tx_axi: AXI-Lite Interface for JESD Tx Physical Layer.

  • Type: devsignal

• phy_rx_axi: AXI-Lite Interface for JESD Rx Physical Layer.

  • Type: devsignal

Subdevice Connections:

• Supported device worker: adrv9371_jesd_2tx_2rx

  
  

  Connections:

  
  

  • Subdevice port: axi_rx_adxcvr

  • Supported worker port: phy_rx_axi

    • Index: None

  
  

  • Subdevice port: axi_tx_adxcvr

  • Supported worker port: phy_tx_axi

    • Index: None

  
  

  • Subdevice port: axi_rx_clkgen

  • Supported worker port: clk_rx_axi

    • Index: None

  
  

  • Subdevice port: axi_tx_clkgen

  • Supported worker port: clk_tx_axi

    • Index: None

  
  

  • Subdevice port: axi_rx_jesd

  • Supported worker port: link_rx_axi

    • Index: None

  
  

  • Subdevice port: axi_tx_jesd

  • Supported worker port: link_tx_axi

    • Index: None

  
  

  • Subdevice port: axi_rx_tpl

  • Supported worker port: tpl_rx_axi

    • Index: None

  
  

  • Subdevice port: axi_tx_tpl

  • Supported worker port: tpl_tx_axi

    • Index: None

  
  

Worker Signals

• ch0

  • Direction: out

  • Differential: false

  • Pin: false

• ch1

  • Direction: out

  • Differential: false

  • Pin: false

• awaddr

  • Direction: out

  • Width: 32

  • Differential: false

  • Pin: false

• awprot

  • Direction: out

  • Width: 3

  • Differential: false

  • Pin: false

• awvalid

  • Direction: out

  • Differential: false

  • Pin: false

• awready

  • Direction: in

  • Differential: false

  • Pin: false

• wdata

  • Direction: out

  • Width: 32

  • Differential: false

  • Pin: false

• wstrb

  • Direction: out

  • Width: 4

  • Differential: false

  • Pin: false

• wvalid

  • Direction: out

  • Differential: false

  • Pin: false

• wready

  • Direction: in

  • Differential: false

  • Pin: false

• bresp

  • Direction: in

  • Width: 2

  • Differential: false

  • Pin: false

• bvalid

  • Direction: in

  • Differential: false

  • Pin: false

• bready

  • Direction: out

  • Differential: false

  • Pin: false

• araddr

  • Direction: out

  • Width: 32

  • Differential: false

  • Pin: false

• arprot

  • Direction: out

  • Width: 3

  • Differential: false

  • Pin: false

• arvalid

  • Direction: out

  • Differential: false

  • Pin: false

• arready

  • Direction: in

  • Differential: false

  • Pin: false

• rdata

  • Direction: in

  • Width: 32

  • Differential: false

  • Pin: false

• rresp

  • Direction: in

  • Width: 2

  • Differential: false

  • Pin: false

• rvalid

  • Direction: in

  • Differential: false

  • Pin: false

• rready

  • Direction: out

  • Differential: false

  • Pin: false

• s_axi_aclk

  • Direction: out

  • Differential: false

  • Pin: false

• s_axi_aresetn

  • Direction: out

  • Differential: false

  • Pin: false