cic_dec_csts HDL Worker

Detail

The HDL implementation of cic_dec_csts device workers, which implements the CIC decimator primitive, with two instances declared, one for the real data values and the second for the imaginary data values.

This device worker implements a BY-PASS Mode: down_sample_factor = 1.

Worker Properties

• VIVADO_ILA_p: Build-time parameter for Xilinx Integrated Logic Analyzer (ILA).

  • Type: bool

  • Access:

    • Parameter: True

    • Writable: False

    • Initial: False

    • Volatile: False

    • Read back: False

  • Default value: None

• ocpi_buffer_size_output: OpenCPI Framework Property.

  • Type: ushort

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: True

    • Volatile: False

    • Read back: False

  • Default value: 0

• ocpi_blocked_output: OpenCPI Framework Property.

  • Type: ulong

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• ocpi_max_latency_output: OpenCPI Framework Property.

  • Type: ushort

  • Access:

    • Parameter: True

    • Writable: False

    • Initial: False

    • Volatile: False

    • Read back: False

  • Default value: None

• ocpi_latency_output: OpenCPI Framework Property.

  • Type: ushort

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• ocpi_messages_output: OpenCPI Framework Property.

  • Type: ulong

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• ocpi_bytes_output: OpenCPI Framework Property.

  • Type: ulong

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

Worker Ports

Inputs:

• input: Input Data Port.

  • Protocol: complex_short_timed_sample

  • Optional: False

Outputs:

• output: Output Data Port.

  • Protocol: complex_short_timed_sample

  • Optional: False