x310 Platform Worker

OpenCPI Ettus USRP X310 platform worker.

The Ettus Research USRP X310 is a high-performance, scalable software defined radio (SDR) platform for designing and deploying next generation wireless communications systems. The hardware architecture combines two extended-bandwidth daughterboard slots covering DC to 6 GHz with up to 160 MHz of baseband bandwidth, multiple high-speed interface options (PCIe, dual 10 GigE, dual 1 GigE), and a large user-programmable Kintex-7 FPGA in a convenient desktop or rack-mountable half-wide 1U form factor.

  • Xilinx Kintex-7 XC7K410T FPGA

  • 14 bit 200 MS/s ADC

  • 16 bit 800 MS/s DAC

  • Frequency range: DC - 6 GHz with suitable daughterboard

  • Up 160MHz bandwidth per channel

  • Two wide-bandwidth RF daughterboard slots

  • Optional GPSDO

  • Multiple high-speed interfaces (Dual 10G, PCIe Express, ExpressCard, Dual 1G)

The Ettus USRP X310 supports a range of plugin daughterboards that contain the baseband to RF frequency modulation, PA and LNA functionality. This platform worker supports the UBX160-160 daughterboard only.

Detail

The x310 platform includes the following device workers

  • time_server

  • dgrdma_config_dev

  • lmk04816

  • x310_gpio

  • ubx160_eeprom

  • dac_spi

One or two instances of the daughter board device workers can be used with this platform. These workers are

  • data_sink_qdac_csts

  • ad9146

  • data_src_qadc_csts

  • ads62p48

  • max2871 (RXLO1, RXLO2, TXLO1, TXLO2)

  • ubx160_cpld

  • ubx160_io

Assemblies can be built using this platform worker that support either one (single) or two (dual) ethernet ports

time_server.hdl

This device worker provides a Time Service Interface to OpenCPI.

dgrdma_config_dev.hdl

This device worker is required when using DGRDMA OpenCPI functionality. DGRDMA provides the necessary functionality for interfacing between OpenCPI software (RCC) and FPGA implementation (HDL) using one or two ethernet interfaces. This worker provides property access used for control and configuration of the OpenCPI DGRDMA components.

lmk04816.hdl

This device worker is used for configuration of the LMK04816 clock generator IC present on the x310 mother board. Configuration of the LMK04816 is performed by the drc_x310.rcc Digital-Radio-Controller worker. It is not necessary for an application using the x310 platform to read or write to the properties of this worker.

x310_gpio.hdl

This device worker provides access to the 12 front-panel GPIO signals (AUX IO connector). This worker is not required for DGRDMA or x310 Digital-radio-controller functionality. It is provided to aid assembly and application development.It provides a means to connect input or output signals to the FPGA for debug and verification purposes.

ubx160_eeprom.hdl

A single instance of this device worker is included in the x310 platform. This provides access to the mother board and daughter board EEPROMs.

dac_spi

This worker is a sub-device of the ad9146.hdl device worker. It provides access to the hardware registers of the DAC ICs over its SPI interface. One instance of this sub-device worker is required to control both DACs. Note also that the DAC SPI uses a separate SPI bus to that used for controlling the ADCs.

One or two instance of the following device workers are used to support the UBX160 daughter board hardware, depending on the number fitted. The worker instance names are prefixed with DB0 or DB1 to distinguish between the two daughter boards.

data_sink_qdac_csts

An instance of this worker is used for each of the two transmit data streams (one for each daughter board). It is used to connect the transmit data stream to the DAC device.

ad9146

The AD9146 is a dual 16-bit digital-to-analogue converter (DAC). There are two AD9146 devices on the x310 mother board. Each device generates the analogue I and Q baseband signals for a single daughter board.

data_src_qadc_csts

An instance of this worker is used for each of the two receive data streams (one for each daughter board). It is used to connect the ADC, producing data on the receive data stream.

ads62p48

The ADS62P48 is a dual 14-bit analogue-to-digital converter (ADC). There are two ADS62P48 devices on the x310 mother board. Each devices digitises the analogue I and Q baseband signals from a single daughter board.

max2871 (RXLO1, RXLO2, TXLO1, TXLO2)

The MAX2871 is an ultra-wideband phase-locked loop (PLL) with integrated voltage control oscillators (VCOs). Each UBX160 daughter board has 4 MAX2871 devices. These are used for generating the transmit (TXLO1/TXLO2) and receiver (RXLO1/RXLO2) clocks.

ubx160_cpld

The ubx160_cpld.hdl device worker provides the means to control the CPLD device on the UBX160 daughter board. This is used to control the signal paths on the UBX160 daughter card.

ubx160_io

The UBX160_io.hdl device worker provides the means to read and write a number of GPIO signals used to control a UBX160 daughter board. The ubx160_io.hdl device worker also contains the implementation of the SPI interface used by the AD9146, ADS62P48 and UBX160_CPLD devices.

Worker Properties

  • ack_tracker_bitfield_width

    • Type: ulong

    • Access:

      • Parameter: True

      • Writable: False

      • Initial: False

      • Volatile: False

      • Read back: False

    • Default value: None

  • ack_tracker_max_ack_count

    • Type: uchar

    • Access:

      • Parameter: True

      • Writable: False

      • Initial: False

      • Volatile: False

      • Read back: False

    • Default value: None

  • dual_ethernet

    • Type: bool

    • Access:

      • Parameter: True

      • Writable: False

      • Initial: False

      • Volatile: False

      • Read back: False

    • Default value: None

  • clock_ref_select

    • Type: enum

      • Allowed values: ['ext', 'int', 'gps']

    • Access:

      • Parameter: True

      • Writable: False

      • Initial: False

      • Volatile: False

      • Read back: False

    • Default value: None

Worker Ports

    Interfaces (other than data I/O ports):

  • dev

    • Type: devsignal

    • Subdevice Connections:

    • Supported device worker: dgrdma_config_dev


      Connections:


      • Subdevice port: dev

      • Supported worker port: dev

        • Index: 0


Worker Signals

  • RESET

    • Direction: out

    • Differential: false

    • Pin: false

  • REMOTE_MAC_ADDR

    • Direction: out

    • Width: 64

    • Differential: false

    • Pin: false

  • REMOTE_DST_ID

    • Direction: out

    • Width: 16

    • Differential: false

    • Pin: false

  • LOCAL_SRC_ID

    • Direction: out

    • Width: 16

    • Differential: false

    • Pin: false

  • INTERFACE_MTU

    • Direction: out

    • Width: 16

    • Differential: false

    • Pin: false

  • ACK_WAIT

    • Direction: out

    • Width: 32

    • Differential: false

    • Pin: false

  • MAX_ACKS_OUTSTANDING

    • Direction: out

    • Width: 8

    • Differential: false

    • Pin: false

  • COALESCE_WAIT

    • Direction: out

    • Width: 32

    • Differential: false

    • Pin: false

  • DUAL_ETHERNET

    • Direction: out

    • Differential: false

    • Pin: false

  • ACK_TRACKER_REJ_ACK

    • Direction: in

    • Differential: false

    • Pin: false

  • ACK_TRACKER_BITFIELD

    • Direction: in

    • Width: 32

    • Differential: false

    • Pin: false

  • ACK_TRACKER_BASE_SEQNO

    • Direction: in

    • Width: 16

    • Differential: false

    • Pin: false

  • ACK_TRACKER_REJ_SEQNO

    • Direction: in

    • Width: 16

    • Differential: false

    • Pin: false

  • ACK_TRACKER_TOTAL_ACKS_SENT

    • Direction: in

    • Width: 32

    • Differential: false

    • Pin: false

  • ACK_TRACKER_TX_ACKS_SENT

    • Direction: in

    • Width: 32

    • Differential: false

    • Pin: false

  • ACK_TRACKER_PKTS_ENQUEUED

    • Direction: in

    • Width: 32

    • Differential: false

    • Pin: false

  • ACK_TRACKER_REJECT_OUT_OF_RANGE

    • Direction: in

    • Width: 32

    • Differential: false

    • Pin: false

  • ACK_TRACKER_REJECT_ALREADY_SET

    • Direction: in

    • Width: 32

    • Differential: false

    • Pin: false

  • ACK_TRACKER_ACCEPTED_BY_PEEK

    • Direction: in

    • Width: 32

    • Differential: false

    • Pin: false

  • ACK_TRACKER_HIGH_WATERMARK

    • Direction: in

    • Width: 16

    • Differential: false

    • Pin: false

  • FRAME_PARSER_REJECT

    • Direction: in

    • Width: 32

    • Differential: false

    • Pin: false

  • REMOTE_IP_ADDR

    • Direction: out

    • Width: 32

    • Differential: false

    • Pin: false

  • REMOTE_UDP_PORT

    • Direction: out

    • Width: 16

    • Differential: false

    • Pin: false

  • FPGA_125MHz_CLK

    • Direction: in

    • Differential: false

    • Pin: true

  • FPGA_REFCLK_10MHz_p

    • Direction: in

    • Differential: false

    • Pin: true

  • FPGA_REFCLK_10MHz_n

    • Direction: in

    • Differential: false

    • Pin: true

  • XG_CLK_p

    • Direction: in

    • Differential: false

    • Pin: true

  • XG_CLK_n

    • Direction: in

    • Differential: false

    • Pin: true

  • TCXO_ENA

    • Direction: out

    • Differential: false

    • Pin: true

  • ClockRefSelect

    • Direction: out

    • Width: 2

    • Differential: false

    • Pin: true

  • aIoResetIn_n

    • Direction: in

    • Differential: false

    • Pin: true

  • aIoReadyOut

    • Direction: out

    • Differential: false

    • Pin: true

  • aIoReadyIn

    • Direction: in

    • Differential: false

    • Pin: true

  • aIoPort2Restart

    • Direction: out

    • Differential: false

    • Pin: true

  • aStc3Gpio7

    • Direction: in

    • Differential: false

    • Pin: true

  • IoRxClock

    • Direction: in

    • Differential: false

    • Pin: true

  • IoRxClock_n

    • Direction: in

    • Differential: false

    • Pin: true

  • irIoRxData

    • Direction: in

    • Width: 16

    • Differential: false

    • Pin: true

  • irIoRxData_n

    • Direction: in

    • Width: 16

    • Differential: false

    • Pin: true

  • irIoRxHeader

    • Direction: in

    • Differential: false

    • Pin: true

  • irIoRxHeader_n

    • Direction: in

    • Differential: false

    • Pin: true

  • IoTxClock

    • Direction: out

    • Differential: false

    • Pin: true

  • IoTxClock_n

    • Direction: out

    • Differential: false

    • Pin: true

  • itIoTxData

    • Direction: out

    • Width: 16

    • Differential: false

    • Pin: true

  • itIoTxData_n

    • Direction: out

    • Width: 16

    • Differential: false

    • Pin: true

  • itIoTxHeader

    • Direction: out

    • Differential: false

    • Pin: true

  • itIoTxHeader_n

    • Direction: out

    • Differential: false

    • Pin: true

  • aIrq

    • Direction: out

    • Differential: false

    • Pin: true

  • SFP0_TX_p

    • Direction: out

    • Differential: false

    • Pin: true

  • SFP0_TX_n

    • Direction: out

    • Differential: false

    • Pin: true

  • SFP0_RX_p

    • Direction: in

    • Differential: false

    • Pin: true

  • SFP0_RX_n

    • Direction: in

    • Differential: false

    • Pin: true

  • SFPP0_RxLOS

    • Direction: in

    • Differential: false

    • Pin: true

  • SFPP0_TxFault

    • Direction: in

    • Differential: false

    • Pin: true

  • SFPP0_TxDisable

    • Direction: out

    • Differential: false

    • Pin: true

  • LED_LINK2

    • Direction: out

    • Differential: false

    • Pin: true

  • LED_ACT2

    • Direction: out

    • Differential: false

    • Pin: true

  • SFP1_TX_p

    • Direction: dual_ethernet ? out : unused

    • Differential: false

    • Pin: true

  • SFP1_TX_n

    • Direction: dual_ethernet ? out : unused

    • Differential: false

    • Pin: true

  • SFP1_RX_p

    • Direction: in

    • Differential: false

    • Pin: true

  • SFP1_RX_n

    • Direction: in

    • Differential: false

    • Pin: true

  • SFPP1_RxLOS

    • Direction: in

    • Differential: false

    • Pin: true

  • SFPP1_TxFault

    • Direction: in

    • Differential: false

    • Pin: true

  • SFPP1_TxDisable

    • Direction: out

    • Differential: false

    • Pin: true

  • LED_LINK1

    • Direction: out

    • Differential: false

    • Pin: true

  • LED_ACT1

    • Direction: out

    • Differential: false

    • Pin: true

  • LED_PPS

    • Direction: out

    • Differential: false

    • Pin: true

  • LED_GPSLOCK

    • Direction: out

    • Differential: false

    • Pin: true

  • LED_LINKSTAT

    • Direction: out

    • Differential: false

    • Pin: true

  • LED_LINKACT

    • Direction: out

    • Differential: false

    • Pin: true

  • FPGA_PUDC_B

    • Direction: in

    • Differential: false

    • Pin: true

Utilization