log_us HDL Worker
Pipelined HDL implementation of logarithm, allowing one input and one output every FPGA clock cycle, with a delay of 24 clock cycles through the pipeline.
Detail
The logarithm primitive produces the logarithm result. The result of the logarithm primitive is scaled by a power of two. The output of the scaling is rounded to the nearest integer by the rounding half-up primitive. As the logarithm result is a 16-bit fixed point value, setting the output scaling factor greater than 16 adds no further precision to the output.
The implementation interprets input values of 0 as a 1. Output values are limited to 65535 if exceeded.
Worker Properties
ocpi_buffer_size_outputType:
ushortAccess:
Parameter:
FalseWritable:
FalseInitial:
TrueVolatile:
FalseRead back:
False
Default value:
0
ocpi_blocked_outputType:
ulongAccess:
Parameter:
FalseWritable:
FalseInitial:
FalseVolatile:
TrueRead back:
False
Default value:
None
ocpi_max_latency_outputType:
ushortAccess:
Parameter:
TrueWritable:
FalseInitial:
FalseVolatile:
FalseRead back:
False
Default value:
None
ocpi_latency_outputType:
ushortAccess:
Parameter:
FalseWritable:
FalseInitial:
FalseVolatile:
TrueRead back:
False
Default value:
None
ocpi_messages_outputType:
ulongAccess:
Parameter:
FalseWritable:
FalseInitial:
FalseVolatile:
TrueRead back:
False
Default value:
None
ocpi_bytes_outputType:
ulongAccess:
Parameter:
FalseWritable:
FalseInitial:
FalseVolatile:
TrueRead back:
False
Default value:
None
Worker Ports
inputProtocol:
ushort_timed_sampleOptional:
False
outputProtocol:
ushort_timed_sampleOptional:
False
Inputs:
Outputs:
Utilisation
Utilization reporting is not currently implemented.