convolutional_interleaver_us HDL Worker
Implementation of a convolutional interleaver.
Detail
The convolutional interleaver worker uses shift registers to implement the delay lines. The shift registers were written to infer an SRL.
The worker allows for setting a port_data_width parameter property to define the widths of the input and output ports.
References:
Worker Properties
port_data_widthType:
ucharAccess:
Parameter:
TrueWritable:
FalseInitial:
FalseVolatile:
FalseRead back:
False
Default value:
None
bit_widthType:
ucharAccess:
Parameter:
TrueWritable:
FalseInitial:
FalseVolatile:
FalseRead back:
False
Default value:
None
ocpi_buffer_size_outputType:
ushortAccess:
Parameter:
FalseWritable:
FalseInitial:
TrueVolatile:
FalseRead back:
False
Default value:
0
ocpi_blocked_outputType:
ulongAccess:
Parameter:
FalseWritable:
FalseInitial:
FalseVolatile:
TrueRead back:
False
Default value:
None
ocpi_max_latency_outputType:
ushortAccess:
Parameter:
TrueWritable:
FalseInitial:
FalseVolatile:
FalseRead back:
False
Default value:
None
ocpi_latency_outputType:
ushortAccess:
Parameter:
FalseWritable:
FalseInitial:
FalseVolatile:
TrueRead back:
False
Default value:
None
ocpi_messages_outputType:
ulongAccess:
Parameter:
FalseWritable:
FalseInitial:
FalseVolatile:
TrueRead back:
False
Default value:
None
ocpi_bytes_outputType:
ulongAccess:
Parameter:
FalseWritable:
FalseInitial:
FalseVolatile:
TrueRead back:
False
Default value:
None
Worker Ports
inputProtocol:
ushort_timed_sampleOptional:
False
outputProtocol:
ushort_timed_sampleOptional:
False
Inputs:
Outputs:
Worker Ports
Inputs:
input: Size defined byport_data_width.Type:
StreamInterfaceProtocol:
ushort_timed_sample-protClock:
outputData width:
port_data_width
Outputs:
output: Size defined byport_data_widthType:
StreamInterfaceProtocol:
ushort_timed_sample-protWorker EOF:
falseInsertEOM:
trueClockDirection:
inData width:
port_data_width
Utilisation
Utilization reporting is not currently implemented.