timestamper HDL Worker

Application worker HDL implementation with a settable runtime configuration parameter for the enable property.

Detail

Worker Properties

• ocpi_buffer_size_out

  • Type: ushort

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: True

    • Volatile: False

    • Read back: False

  • Default value: 0

• ocpi_blocked_out

  • Type: ulong

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• ocpi_max_latency_out

  • Type: ushort

  • Access:

    • Parameter: True

    • Writable: False

    • Initial: False

    • Volatile: False

    • Read back: False

  • Default value: None

• ocpi_latency_out

  • Type: ushort

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• ocpi_messages_out

  • Type: ulong

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

• ocpi_bytes_out

  • Type: ulong

  • Access:

    • Parameter: False

    • Writable: False

    • Initial: False

    • Volatile: True

    • Read back: False

  • Default value: None

Worker Ports

Inputs:

• in: Signed complex samples.

  • Protocol: iqstream

  • Optional: False

Outputs:

• out: Signed complex samples.

  • Protocol: iqstream_with_sync

  • Optional: False

Interfaces (other than data I/O ports):

• time: Time interface provided by OpenCPI time server.

  • Type: timeinterface

Control Timing and Signals

The timestamper HDL worker uses the clock from the control plane and standard control signals.

Data presented on the input appears on the output clock three cycles later (latency=3). Two of the three clock cycles consist of a time message.

Utilization

Utilization reporting is not currently implemented.