Half-even rounder (rounding_halfeven)

Half-even rounding and truncation for a variable width signed input. This rounding mode is also known as bankers rounding or convergent rounding.

Design

In the half-even rounder the input stream is processed based on the following rules:

  • If binary point bit is zero, (therefore the number is even) the number is shifted right by the number of places to be truncated (rounded-down). The number is then truncated to the output width.

  • If binary point bit is one, (therefore the number is odd) the input is right shifted by the number of places to be truncated less one, one is added, and then the input is right shifted by one. The number is then truncated to the output width.

Implementation

The primitive is pipelined so that a new sample can be inserted into the primitive on every rising edge of clk. The data_valid_in signal allows each input sample to be marked as valid or not. The pipeline advances every rising edge of clk regardless of if valid data is passed to the primitive or not. The data_valid_out signal is a delayed version of data_valid_in that indicates valid output samples.

The clk_en signal provides a clock enable for the primitive. When clk_en is set low no data will enter or leave the primitive and all calculations are stopped. When clk_en is high the module will operate normally.

Interface

Generics

  • input_width_g (integer): Sets width of data_in signal.

  • output_width_g (integer): Sets width of data_out signal.

  • saturation_en_g (boolean): Enables saturation on data when rounding has caused an overflow.

Ports

  • clk (std_logic), in: Clock. Inputs and outputs registered on rising edge.

  • rst (std_logic), in: Reset. Active high, synchronous with rising edge of clock.

  • clk_en (std_logic), in: Clock Enable. If low the module will not operate.

  • data_in (signed, input_width_g bits), in: Input value for primitive.

  • data_valid_in (std_logic), in: data_in is valid when data_valid_in is high.

  • binary_point (integer), in: Sets number of times the input data is right shifted before being output.

  • data_out (signed, output_width_g bits), out: Output value for primitive.

  • data_valid_out (std_logic), out: data_out is valid when data_valid_out is high.

Dependencies

The dependencies to other elements in OpenCPI are:

  • None.

There is also a dependency on:

  • ieee.std_logic_1164

  • ieee.numeric_std

Limitations

Limitations of rounding_halfeven are:

  • None