log_us HDL worker

Pipelined HDL implementation of logarithm, allowing one input and one output every FPGA clock cycle, with a delay of 24 clock cycles through the pipeline.

Detail

The logarithm primitive produces the logarithm result. The result of the logarithm primitive is scaled by a power of two. The output of the scaling is rounded to the nearest integer by the rounding half-up primitive. As the logarithm result is a 16-bit fixed point value, setting the output scaling factor greater than 16 adds no further precision to the output.

The implementation interprets input values of 0 as a 1. Output values are limited to 65535 if exceeded.

Worker Ports

Inputs:

• input

  • Type: streaminterface

  • Data width: 16

  • Protocol: ushort_timed_sample-prot

  • Optional: False

Outputs:

• output

  • Type: streaminterface

  • Data width: 16

  • Protocol: ushort_timed_sample-prot

  • Optional: False

Utilisation