exp_us HDL worker

Pipelined HDL implementation of exponentiation, allowing one input and one output every FPGA clock cycle, with a delay of 36 clock cycles through the pipeline.

Detail

The input scaling factor \(N\) can be set anywhere from 0 to 16 without any loss being introduced by the HDL implementation. As the exponentiation primitive is designed for UQ16.16 fixed point input values and UQ16.16 fixed point output values. With the output of the exponentiation primitive passed to a rounding half-up primitive instance where the output value is rounded to the nearest integer (0.5 rounded up) and the 16 fractional bits thrown away.

Worker Ports

    Inputs:

  • input

    • Type: streaminterface

    • Data width: 16

    • Protocol: ushort_timed_sample-prot

    • Optional: False

    • Outputs:

  • output

    • Type: streaminterface

    • Data width: 16

    • Protocol: ushort_timed_sample-prot

    • Optional: False

Utilisation