adder_s HDL worker

Detail

The adder is fully pipelined and can take a new input on every clock edge. If sample opcode message data is only available on a single input port, backpressure is applied to the input port with sample opcode message data until the other input port has sample data available.

Worker Ports

Inputs:

• input_1

  • Type: streaminterface

  • Data width: 16

  • Protocol: short_timed_sample-prot

  • Optional: False

• input_2

  • Type: streaminterface

  • Data width: 16

  • Protocol: short_timed_sample-prot

  • Optional: False

Outputs:

• output

  • Type: streaminterface

  • Data width: 16

  • Protocol: short_timed_sample-prot

  • Optional: False

Utilisation