register_ul HDL worker

Detail

Worker Ports

Inputs:

• input

  • Type: streaminterface

  • Data width: 32

  • Protocol: ulong_timed_sample-prot

  • Optional: False

Outputs:

• output

  • Type: streaminterface

  • Data width: 32

  • Protocol: ulong_timed_sample-prot

  • Optional: False

Utilisation