In https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf, Figure 10-1 and Table 10-1 describes the master AXI port, M_AXI_HPM0_FPD,  (which is used for OCPI Control Plane) as having an address of 0xA4000000 or potentially 0xA0000000 if VCU is mapped else where.

So why in runtime/hdl/include/HdlZynq.h is M_HP0_PADDR (i.e. M_AXI_HPM0_FPD from the TRM) = 0xA8000000?