Hi Roland,
As discussed separately, the E310 serial port does not expose the JTAG port
of the device.
To gain access to this, you do have to remove the shell and use a custom
connector.
In the interest of documenting this as I imagine others may hit this, I'm
going to make a post on the forum (opencpi.dev).
Cheers,
Dom
On Tue, Dec 5, 2023 at 8:08 AM roland.johnson--- via discuss <
discuss_at_lists.opencpi.org> wrote:
> Hi everyone,
>
> Has anyone here be successful in integrating a Xilinx ILA IP core into an
> Ettus E310?
>
> Following on from Brian Padalino’s thread a few years ago about
> implementing a Xilinx ILA IP block in OpenCPI, I’m having a similar issue
> though perhaps for a different target platform. I’ve followed through the
> documentation here:
> https://opencpi.gitlab.io/releases/v2.4.6/docs/Debugging_Tools_Guide.pdf
> following Case 1: “Instance a Debug ILA in an HDL Worker using cores from
> Vivado’s IP Catalogâ€.
>
> I’ve managed to implement the IP, build the component, OHAD and OAS, and
> deploy the application onto an Ettus E310 in standalone mode (all the
> necessary files are on the SD card and it operates independently of any
> resources in CentOS), and the application does run, and is verifiable by a
> “file_write†worker at the output.
>
> However, when I try to connect to the Zynq SoC inside the Ettus E310, my
> version of Vivado (2019.2) can’t see the SoC. I don’t know if this is to be
> expected, as the output of the E310 is either an ethernet cable or serial
> console cable over UART, or if it’s necessarily an OpenCPI problem. At any
> rate, I can’t connect to the device. I’m going to try to connect directly
> to the JTAG connector (by dismantling the E310 box slightly), so I’ll
> report back with any findings I have there.
>
> Best,
> Roland
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Received on Tue Dec 05 2023 - 14:08:15 CST