On Wed, Aug 5, 2020 at 12:42 PM Davis Hoover <dhoover_at_geontech.com> wrote:
> The error suggests you are routing clock signals from multiple regions
> (each region corresponding to an adc_sub instance) to a single location,
> which is not possible. Assuming you inserted an ILA into the worker EDF,
> I'm not sure why the placement algorithm would be considering the
> routability of a BUFR from a separate worker instance... but it may be
> worth double checking that the signals in your ILA include those from only
> a single adc_sub.
>
I am using method 3.1.2 as described here:
https://opencpi.gitlab.io/releases/v1.7.0/docs/Debugging_Tools_Guide.pdf
Your statement about double checking that the signals in my ILA include
only a single adc_sub sounds difficult for me to do. I imagine there are
going to be 2 ILA's instantiated since there are 2 adc_sub's instantiated
which are instrumented for debug.
>
> The "Clock Rule" sections don't seem relevant since they all have "Status:
> PASS".
>
Agreed.
>
> Some background info:
> BUFRs were originally chosen due to their high performance on Zynq 7 Series
> - performance which was necessary for the >240MHz data I/O clock for AD936x
> LVDS mode. The output of BUFRs can only be routed within a single clock
> region (7 series die is separated into 6 regions).
>
So it seems that maybe the way the ILA was resolved got Vivado confused
regarding clocks and what is actually accessing the ILA?
Do you think I should try a BUFG instead of a BUFR? Or do you think I
should modify the adc_sub to include a DEBUG parameter and modify the build
that has the DEBUG parameter that is true for usage?
As an aside, is there a better way to do this? Would it be easier to mark
the signals in the code using a generic or something? I'd love to be able
to work from all source and not worry about all these EDIF netlists, but I
know that isn't feasible.
Brian
Received on Wed Aug 05 2020 - 17:15:49 CDT