I have a design I am trying to debug the AD9361 ADC interface. I am
following the guide here:
https://opencpi.gitlab.io/releases/v1.7.0/docs/Debugging_Tools_Guide.pdf
For 3.1.2 - inserting the debug cores into the EDIF netlist. I save off
the netlist and debug probe file and things seem OK.
My platform has two AD9361 devices in it. When I try to build a target
assembly with both of them instantiated, I get an error regarding the debug
cores. Specifically that there are duplicates.
I am going to attempt to debug my design slightly differently, but is this
expected in the way that the debug core is created and attached to the EDIF
netlist? Will both try to attach to JTAG instead of chaining appropriately?
Does anyone else have experience debugging OpenCPI netlists that have the
same debug instrumented core instantiated multiple times?
Thanks,
Brian
Received on Tue Aug 04 2020 - 19:19:03 CDT