Re: [Discuss OpenCPI] Fwd: Fwd: AD9361 LVDS Interface Delays

From: Aaron Olivarez <aaron_at_olivarez.info>
Date: Wed, 29 Jul 20 19:32:40 -0500

Brian,

Attached is the data you requested.

On Wed, Jul 29, 2020 at 3:19 PM Brian Padalino <bpadalino_at_gmail.com> wrote:

> Hey Aaron,
>
> On Wed, Jul 29, 2020 at 4:11 PM Aaron Olivarez <aaron_at_olivarez.info>
> wrote:
>
>> Brian,
>>
>> I just tested the ad9361_adc_test application on Zedboard/FMCOMMS2
>> platform
>> and it reported 0% BER.
>>
>
> Thanks for spot checking for me. Just curious, can you show the eye
> diagram of the resulting clock/data timing offsets from the odata
> directory? I am curious what typical bit error rates you get as the eye
> moves.
>
>
>>
>> Since version 1.7.0 we're moving away from these tests and have added
>> newer
>> tests called: data_src_qadc_test and data_sink_qdac_tests that utilize the
>> new split clocking ADC/DAC paradigm for AD9361 transceiver. We have
>> examples available for the following platforms: Zedboard/FMCOMM2/3, E310,
>> and ZCU104.
>>
>
> Thanks for the info. I'll try to switch over to those tests.
>
> Brian
>


Received on Thu Jul 30 2020 - 00:32:40 CDT