I am trying to add a new LFSR configuration to the data_src.hdl component.
The following is the configuration that I added to the build file:
<configuration id='2'>
<parameter name="DATA_BIT_WIDTH_p" Value="16"/>
<parameter name="LFSR_POLYNOMIAL_p"
Value='1,1,0,1,0,0,0,0,0,0,0,0,1,0,0,0'/> <!-- x^16 + x^15 + x^13 + x^4 +
1(implied) -->
<parameter name="LFSR_SEED_p" Value='1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1'/>
<parameter name="ZLM_WHEN_NUM_SAMPLES_REACHED_p" Value="false"/>
<parameter name='ODATA_WIDTH_p' value='16'/>
</configuration>
My goal was to use the LFSR to feed into the msk_mapper, which is why I
wanted 16-bit input and output.
The problem I have is that I run into this synthesis issue:
ERROR: [Synth 8-690] width mismatch in assignment; target has 12 bits,
source has 16 bits
I look at the source and it's a line that looks like this:
LFSR_POLYNOMIAL_p : in std_logic_vector(12*(1)-1 downto 0) :=
ocpi.types.slv(Bool_array_t(work.data_src_constants.LFSR_POLYNOMIAL_p));
The really weird part is the 12 there. Looking at the data_src-spec file,
the default width is DATA_BIT_WIDTH_p, which I've set to a value of 16.
So I tried switching the order of the configurations and it seems
DATA_BIT_WIDTH_p is sticky for all following configurations. If I have a
16-bit starting configuration, I get a mismatch on building a 12-bit
configuration.
This is all in code generation, so I am not sure where to fix something
like this. Guidance is appreciated.
Thanks,
Brian
Received on Fri Apr 17 2020 - 04:02:14 CDT