In the ad9361_data_sub HDL worker, there are the following LVDS interface
delays listed:
- DATA_CLK_Delay
- RX_Data_Delay
- FB_CLK_Delay
- TX_Data_Delay
Under the build XML file, it seems that these values need to be built for
every variant that could possibly come up. This seems problematic since
the values may be suboptimal for different sampling frequencies.
I also see in the ad9361_config_proxy-spec.xml file, that for the
ad9361_init struct, the same delays live there.
When I've worked with these devices under linux in the past, ADI had a
dynamic way they found/configured these values:
https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/interface_timing_validation
So, now to my questions:
- Is there a program somewhere, using OpenCPI, that performs the same
dynamic eye checking to find optimal delays for the AD9361?
- Is there a reason that the ad9361_data_sub is built multiple times with
different default delays when it can be set dynamically for each radio?
Thanks,
Brian
Received on Fri Mar 27 2020 - 15:53:06 CDT