Re: [Discuss OpenCPI] Zynq HDL Primitive Modification

From: Brian Padalino <bpadalino_at_gmail.com>
Date: Thu, 09 Jan 20 11:38:02 -0500

On Thu, Jan 9, 2020 at 11:30 AM Aaron Olivarez <aaron_at_olivarez.info> wrote:

> I made the same modifications, and will be included in OpenCPI release 1.7
> or sooner. We're still in the process of transitioning the project from
> GitHub to GitLab. When the GitLab project is released to the public with
> OpenCPI 1.6 it will include a new contributing guide which layouts the
> steps necessary to push changes back to the community.
>

Awesome!


>
> Looks like your running into the same problems I had to run through. Can
> you elaborate a little more on your setup? In a previous email you
> mentioned you created an RCC platform based on Xilinx 2017.4. Did you
> updated the stock firmware and have that running on Pluto? Are you still
> utilizing the USB device functionality orr are you using it in standalone
> mode?
>

I'm only looking to run it standalone. I saw the failure of the fsk_filerw
to target the 7010, so I just excluded it from the list to build for now.
Is there a good internal loopback test to run for OpenCPI that tests AXI
DMA and make sure everything is all plumbed together well? A simple PL
loopback might work well for me? Maybe putting in the TX-only part of the
FSK modem might be the next step? I'm open to suggestions.

My initial plan was just to insmod the kernel module built against the
pluto-fw linux kernel, copy over the appropriate libraries and run a simple
application. Is that not a great idea?

Guidance is very much appreciated.

Thanks,
Brian


Received on Thu Jan 09 2020 - 16:38:02 CST

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