[Discuss OpenCPI] AXI Data Width to 128 for SDP - Zynq UltraScale+

From: David Banks <dbanks_at_geontech.com>
Date: Wed, 30 Jan 19 08:46:27 -0500

Hi OpenCPI experts,

The Zynq UltraScale+ MPSoC supports data-widths up to 128 bits for each
PS-slave AXI HP interface. For now, I configured this down to 64 since that
is the AXI data-width already used by Zynq platforms connected to OpenCPI's
SDP.

I am curious what work would be involved to support the full AXI data-width
of 128 bits for Zynq UltraScale+. I am hesitant to assume it would be as
simple as just changing the AXI package to use 128 data bits for the PS
slave interfaces. Would SDP (sdp2axi) itself have to change to support such
a change, or would it just need to be parametrized differently?

Thanks,
David Banks
dbanks_at_geontech.com
Geon Technologies, LLC


Received on Wed Jan 30 2019 - 13:46:27 CST