[Discuss OpenCPI] FSK filerw and its component UUTs failing on Zynq UltraScale+

From: David Banks <dbanks_at_geontech.com>
Date: Thu, 10 Jan 19 14:46:34 -0500

Hi,

So far, I have ptest, tb_bias_v2 and testbias working on the zcu111/zcu102
Zynq UltraScale devices. I also have verified some custom apps against zed
(pattern_v2->file_write, file_read->capture_v2, and data_src->file_write).
However, FSK filerw is failing.

Here is a visual diff of the hexdump between zcu111 and zed for the
fsk_filerw output:
[image: image.png]

And here are the plotted outputs (zed on top, zcu111 below):
[image: image.png]

I decided to drill down to the individual component unit tests. I am still
building some of them, but here are my results so far:
PASSING: fir_real/complex_sse, complex_mixer, phase_to_amp_cordic, and all
RCC uuts
FAILING: dc_offset_filter, iq_imbalance_fixer, pr_cordic, and rp_cordic

And here are plots of the results for dc_offset_filter and
iq_imbalance_fixer on both zed and zcu111 (inputs on top, outputs below in
each image):
*dc_offset_filter on zed:*
[image: image.png]

*vs dc_offset_filter on zcu111:*
[image: image.png]

*Here, I zoom into the time plot on zcu111:*
[image: image.png]


*And then for iq_imbalance on zed:*
[image: image.png]

*and iq_imbalance_fixer on zcu111:*
[image: image.png]

I have also examined the worker, assembly and container synthesis logs as
well as the implementation logs for these tests and compared them to zed. I
saw nothing worrisome there.

I am using python version 2.7.5 to plot all of these results.

From the hexdump as well as these plots, it looks like we are getting some
bits erroneously flipped to 0 in these tests and in FSK filerw.

Any ideas for debugging this issue? I am branched off of release_1.4.

Thanks!
David Banks
dbanks_at_geontech.com
Geon Technologies, LLC


Received on Thu Jan 10 2019 - 19:46:34 CST