Hi,
I'm trying to use libraries in a project, but facing some issues. I followed chapter 5 of OpenCPI_HDL_Development.pdf guide to describe my library. It's a primitive library written in VHDL.
When I try to build the project (ocpidev build --hdl-platform xsim), it looks like the library is not correctly found and I get the following errors:
=============Building assembly sms_assembly
make[2]: Entering directory `/home/training/SmsProject/hdl/assemblies/sms_assembly'
Building the sms_assembly assembly for xsim (target-xsim/sms_assembly) 0:(ocpi_endian=little ocpi_debug=false)
ERROR: [VRFC 10-213] Registering Dependencies Error: The primary unit 'sms_adder_lib' could not be found during restore
ERROR: [VRFC 10-147] adder_test.adder_test_worker failed to restore
ERROR: [VRFC 10-213] Registering Dependencies Error: The primary unit 'adder_test_worker' could not be found during restore
ERROR: [VRFC 10-147] adder_test.adder_test_rv failed to restore
ERROR: [VRFC 10-213] Registering Dependencies Error: The primary unit 'adder_test_rv' could not be found during restore
ERROR: [VRFC 10-147] adder_test.adder_test failed to restore
ERROR: [VRFC 10-2063] Module <adder_test> not found while processing module instance <adder_test> [/home/training/SmsProject/hdl/assemblies/sms_assembly/gen/sms_assembly-assy.v:56]
ERROR: [VRFC 10-2063] Module <file_write> not found while processing module instance <file_write> [/home/training/SmsProject/hdl/assemblies/sms_assembly/gen/sms_assembly-assy.v:86]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
Error: xsim failed(1). See target-xsim/sms_assembly-xsim.out. 0:01.07 at 15:00:45
make[2]: *** [target-xsim/sms_assembly] Error 1
make[2]: Leaving directory `/home/training/SmsProject/hdl/assemblies/sms_assembly'
make[1]: *** [sms_assembly] Error 2
make[1]: Leaving directory `/home/training/SmsProject/hdl/assemblies'
make: *** [hdlassemblies] Error 2
I'm using OpenCPI v1.3.1.
I'm now stucked with this error, I read the pdf guide again and again but I cannot find what's wrong with my design.
Have I missed a step somewhere?
Thanks,
Sebastien
Received on Mon Sep 24 2018 - 13:29:26 CDT